pinctrl: single: Add support for wake-up interrupts
The pin control registers can have interrupts for example for device wake-up. These interrupts can be treated as a chained interrupt controller as suggested earlier by Linus Walleij <linus.walleij@linaro.org>. This patch adds support for interrupts in a way that should be pretty generic, and works for the omaps that support wake-up interrupts. On omaps, there's an interrupt enable and interrupt status bit for each pin. The two pinctrl domains on omaps share a single interrupt from the PRM chained interrupt handler. Support for other similar hardware should be easy to add. Note that this patch does not attempt to handle the wake-up interrupts automatically unlike the earlier patches. This patch allows the device drivers to do a request_irq() on the wake-up pins as needed. I'll try to do also a separate generic patch for handling the wake-up events automatically. Also note that as this patch makes the pinctrl-single an irq controller, the current bindings need some extra trickery to use interrupts from two different interrupt controllers for the same driver. So it might be worth waiting a little on the patches enabling the wake-up interrupts from drivers as there should be a generic way to handle it coming. And also there's been discussion of interrupts-extended binding for using interrupts from multiple interrupt controllers. In any case, this patch should be ready to go allowing handling the wake-up interrupts in a generic way, or separately from the device drivers. Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Prakash Manjunathappa <prakash.pm@ti.com> Cc: Roger Quadros <rogerq@ti.com> Cc: linux-kernel@vger.kernel.org Cc: Benoît Cousson <bcousson@baylibre.com> Cc: devicetree@vger.kernel.org Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Reviewed-by: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>hifive-unleashed-5.1
Tony Lindgren
parent
02e483f66d
commit
3e6cee1786
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@ -72,6 +72,13 @@ Optional properties:
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/* pin base, nr pins & gpio function */
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pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
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- interrupt-controller : standard interrupt controller binding if using
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interrupts for wake-up events for example. In this case pinctrl-single
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is set up as a chained interrupt controller and the wake-up interrupts
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can be requested by the drivers using request_irq().
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- #interrupt-cells : standard interrupt binding if using interrupts
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This driver assumes that there is only one register for each pin (unless the
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pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
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specified in the pinctrl-bindings.txt document in this directory.
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@ -121,6 +128,8 @@ pmx_core: pinmux@4a100040 {
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reg = <0x4a100040 0x0196>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xffff>;
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};
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@ -131,6 +140,8 @@ pmx_wkup: pinmux@4a31e040 {
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reg = <0x4a31e040 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xffff>;
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};
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@ -15,10 +15,14 @@
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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@ -152,9 +156,15 @@ struct pcs_name {
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/**
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* struct pcs_soc_data - SoC specific settings
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* @flags: initial SoC specific PCS_FEAT_xxx values
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* @irq: optional interrupt for the controller
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* @irq_enable_mask: optional SoC specific interrupt enable mask
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* @irq_status_mask: optional SoC specific interrupt status mask
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*/
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struct pcs_soc_data {
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unsigned flags;
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int irq;
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unsigned irq_enable_mask;
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unsigned irq_status_mask;
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};
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/**
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@ -165,6 +175,7 @@ struct pcs_soc_data {
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* @dev: device entry
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* @pctl: pin controller device
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* @flags: mask of PCS_FEAT_xxx values
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* @lock: spinlock for register access
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* @mutex: mutex protecting the lists
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* @width: bits per mux register
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* @fmask: function register mask
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@ -179,6 +190,9 @@ struct pcs_soc_data {
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* @pingroups: list of pingroups
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* @functions: list of functions
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* @gpiofuncs: list of gpio functions
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* @irqs: list of interrupt registers
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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* @ngroups: number of pingroups
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* @nfuncs: number of functions
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* @desc: pin controller descriptor
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@ -192,7 +206,11 @@ struct pcs_device {
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struct device *dev;
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struct pinctrl_dev *pctl;
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unsigned flags;
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#define PCS_QUIRK_SHARED_IRQ (1 << 2)
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#define PCS_FEAT_IRQ (1 << 1)
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#define PCS_FEAT_PINCONF (1 << 0)
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struct pcs_soc_data socdata;
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raw_spinlock_t lock;
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struct mutex mutex;
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unsigned width;
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unsigned fmask;
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@ -208,6 +226,9 @@ struct pcs_device {
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struct list_head pingroups;
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struct list_head functions;
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struct list_head gpiofuncs;
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struct list_head irqs;
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struct irq_chip chip;
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struct irq_domain *domain;
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unsigned ngroups;
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unsigned nfuncs;
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struct pinctrl_desc desc;
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@ -215,6 +236,8 @@ struct pcs_device {
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void (*write)(unsigned val, void __iomem *reg);
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};
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#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
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#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
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#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
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static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
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@ -440,9 +463,11 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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for (i = 0; i < func->nvals; i++) {
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struct pcs_func_vals *vals;
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unsigned long flags;
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unsigned val, mask;
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vals = &func->vals[i];
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raw_spin_lock_irqsave(&pcs->lock, flags);
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val = pcs->read(vals->reg);
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if (pcs->bits_per_mux)
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@ -453,6 +478,7 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
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val &= ~mask;
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val |= (vals->val & mask);
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pcs->write(val, vals->reg);
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raw_spin_unlock_irqrestore(&pcs->lock, flags);
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}
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return 0;
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@ -494,13 +520,16 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
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for (i = 0; i < func->nvals; i++) {
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struct pcs_func_vals *vals;
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unsigned long flags;
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unsigned val;
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vals = &func->vals[i];
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raw_spin_lock_irqsave(&pcs->lock, flags);
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val = pcs->read(vals->reg);
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val &= ~pcs->fmask;
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val |= pcs->foff << pcs->fshift;
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pcs->write(val, vals->reg);
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raw_spin_unlock_irqrestore(&pcs->lock, flags);
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}
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}
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@ -1450,12 +1479,34 @@ static void pcs_free_pingroups(struct pcs_device *pcs)
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mutex_unlock(&pcs->mutex);
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}
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/**
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* pcs_irq_free() - free interrupt
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* @pcs: pcs driver instance
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*/
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static void pcs_irq_free(struct pcs_device *pcs)
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{
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struct pcs_soc_data *pcs_soc = &pcs->socdata;
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if (pcs_soc->irq < 0)
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return;
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if (pcs->domain)
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irq_domain_remove(pcs->domain);
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if (PCS_QUIRK_HAS_SHARED_IRQ)
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free_irq(pcs_soc->irq, pcs_soc);
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else
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irq_set_chained_handler(pcs_soc->irq, NULL);
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}
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/**
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* pcs_free_resources() - free memory used by this driver
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* @pcs: pcs driver instance
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*/
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static void pcs_free_resources(struct pcs_device *pcs)
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{
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pcs_irq_free(pcs);
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if (pcs->pctl)
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pinctrl_unregister(pcs->pctl);
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@ -1504,6 +1555,256 @@ static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
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}
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return ret;
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}
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/**
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* @reg: virtual address of interrupt register
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* @hwirq: hardware irq number
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* @irq: virtual irq number
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* @node: list node
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*/
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struct pcs_interrupt {
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void __iomem *reg;
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irq_hw_number_t hwirq;
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unsigned int irq;
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struct list_head node;
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};
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/**
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* pcs_irq_set() - enables or disables an interrupt
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*
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* Note that this currently assumes one interrupt per pinctrl
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* register that is typically used for wake-up events.
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*/
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static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
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int irq, const bool enable)
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{
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struct pcs_device *pcs;
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struct list_head *pos;
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unsigned mask;
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pcs = container_of(pcs_soc, struct pcs_device, socdata);
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list_for_each(pos, &pcs->irqs) {
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struct pcs_interrupt *pcswi;
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unsigned soc_mask;
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pcswi = list_entry(pos, struct pcs_interrupt, node);
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if (irq != pcswi->irq)
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continue;
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soc_mask = pcs_soc->irq_enable_mask;
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raw_spin_lock(&pcs->lock);
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mask = pcs->read(pcswi->reg);
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if (enable)
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mask |= soc_mask;
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else
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mask &= ~soc_mask;
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pcs->write(mask, pcswi->reg);
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raw_spin_unlock(&pcs->lock);
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}
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}
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/**
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* pcs_irq_mask() - mask pinctrl interrupt
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* @d: interrupt data
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*/
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static void pcs_irq_mask(struct irq_data *d)
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{
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struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
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pcs_irq_set(pcs_soc, d->irq, false);
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}
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/**
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* pcs_irq_unmask() - unmask pinctrl interrupt
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* @d: interrupt data
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*/
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static void pcs_irq_unmask(struct irq_data *d)
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{
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struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
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pcs_irq_set(pcs_soc, d->irq, true);
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}
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/**
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* pcs_irq_set_wake() - toggle the suspend and resume wake up
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* @d: interrupt data
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* @state: wake-up state
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*
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* Note that this should be called only for suspend and resume.
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* For runtime PM, the wake-up events should be enabled by default.
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*/
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static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
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{
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if (state)
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pcs_irq_unmask(d);
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else
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pcs_irq_mask(d);
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return 0;
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}
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/**
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* pcs_irq_handle() - common interrupt handler
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* @pcs_irq: interrupt data
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*
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* Note that this currently assumes we have one interrupt bit per
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* mux register. This interrupt is typically used for wake-up events.
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* For more complex interrupts different handlers can be specified.
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*/
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static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
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{
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struct pcs_device *pcs;
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struct list_head *pos;
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int count = 0;
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pcs = container_of(pcs_soc, struct pcs_device, socdata);
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list_for_each(pos, &pcs->irqs) {
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struct pcs_interrupt *pcswi;
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unsigned mask;
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pcswi = list_entry(pos, struct pcs_interrupt, node);
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raw_spin_lock(&pcs->lock);
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mask = pcs->read(pcswi->reg);
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raw_spin_unlock(&pcs->lock);
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if (mask & pcs_soc->irq_status_mask) {
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generic_handle_irq(irq_find_mapping(pcs->domain,
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pcswi->hwirq));
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count++;
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}
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}
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return count;
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}
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/**
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* pcs_irq_handler() - handler for the shared interrupt case
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* @irq: interrupt
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* @d: data
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*
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* Use this for cases where multiple instances of
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* pinctrl-single share a single interrupt like on omaps.
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*/
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static irqreturn_t pcs_irq_handler(int irq, void *d)
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{
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struct pcs_soc_data *pcs_soc = d;
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return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
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}
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/**
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* pcs_irq_handle() - handler for the dedicated chained interrupt case
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* @irq: interrupt
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* @desc: interrupt descriptor
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*
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* Use this if you have a separate interrupt for each
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* pinctrl-single instance.
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*/
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static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
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struct irq_chip *chip;
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int res;
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chip = irq_get_chip(irq);
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chained_irq_enter(chip, desc);
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res = pcs_irq_handle(pcs_soc);
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/* REVISIT: export and add handle_bad_irq(irq, desc)? */
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chained_irq_exit(chip, desc);
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return;
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}
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static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct pcs_soc_data *pcs_soc = d->host_data;
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struct pcs_device *pcs;
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struct pcs_interrupt *pcswi;
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pcs = container_of(pcs_soc, struct pcs_device, socdata);
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pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
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if (!pcswi)
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return -ENOMEM;
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pcswi->reg = pcs->base + hwirq;
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pcswi->hwirq = hwirq;
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pcswi->irq = irq;
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mutex_lock(&pcs->mutex);
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list_add_tail(&pcswi->node, &pcs->irqs);
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mutex_unlock(&pcs->mutex);
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irq_set_chip_data(irq, pcs_soc);
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irq_set_chip_and_handler(irq, &pcs->chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops pcs_irqdomain_ops = {
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.map = pcs_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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/**
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* pcs_irq_init_chained_handler() - set up a chained interrupt handler
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* @pcs: pcs driver instance
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* @np: device node pointer
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*/
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static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
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struct device_node *np)
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{
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struct pcs_soc_data *pcs_soc = &pcs->socdata;
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const char *name = "pinctrl";
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int num_irqs;
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if (!pcs_soc->irq_enable_mask ||
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!pcs_soc->irq_status_mask) {
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pcs_soc->irq = -1;
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return -EINVAL;
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}
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INIT_LIST_HEAD(&pcs->irqs);
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pcs->chip.name = name;
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pcs->chip.irq_ack = pcs_irq_mask;
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pcs->chip.irq_mask = pcs_irq_mask;
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pcs->chip.irq_unmask = pcs_irq_unmask;
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pcs->chip.irq_set_wake = pcs_irq_set_wake;
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if (PCS_QUIRK_HAS_SHARED_IRQ) {
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int res;
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res = request_irq(pcs_soc->irq, pcs_irq_handler,
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IRQF_SHARED | IRQF_NO_SUSPEND,
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name, pcs_soc);
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if (res) {
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pcs_soc->irq = -1;
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return res;
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}
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} else {
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irq_set_handler_data(pcs_soc->irq, pcs_soc);
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irq_set_chained_handler(pcs_soc->irq,
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pcs_irq_chain_handler);
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}
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/*
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* We can use the register offset as the hardirq
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* number as irq_domain_add_simple maps them lazily.
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* This way we can easily support more than one
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* interrupt per function if needed.
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*/
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num_irqs = pcs->size;
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pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
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&pcs_irqdomain_ops,
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pcs_soc);
|
||||
if (!pcs->domain) {
|
||||
irq_set_chained_handler(pcs_soc->irq, NULL);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int pinctrl_single_suspend(struct platform_device *pdev,
|
||||
|
|
@ -1549,12 +1850,14 @@ static int pcs_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
}
|
||||
pcs->dev = &pdev->dev;
|
||||
raw_spin_lock_init(&pcs->lock);
|
||||
mutex_init(&pcs->mutex);
|
||||
INIT_LIST_HEAD(&pcs->pingroups);
|
||||
INIT_LIST_HEAD(&pcs->functions);
|
||||
INIT_LIST_HEAD(&pcs->gpiofuncs);
|
||||
soc = match->data;
|
||||
pcs->flags = soc->flags;
|
||||
memcpy(&pcs->socdata, soc, sizeof(*soc));
|
||||
|
||||
PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
|
||||
"register width not specified\n");
|
||||
|
|
@ -1642,6 +1945,16 @@ static int pcs_probe(struct platform_device *pdev)
|
|||
if (ret < 0)
|
||||
goto free;
|
||||
|
||||
pcs->socdata.irq = irq_of_parse_and_map(np, 0);
|
||||
if (pcs->socdata.irq)
|
||||
pcs->flags |= PCS_FEAT_IRQ;
|
||||
|
||||
if (PCS_HAS_IRQ) {
|
||||
ret = pcs_irq_init_chained_handler(pcs, np);
|
||||
if (ret < 0)
|
||||
dev_warn(pcs->dev, "initialized with no interrupts\n");
|
||||
}
|
||||
|
||||
dev_info(pcs->dev, "%i pins at pa %p size %u\n",
|
||||
pcs->desc.npins, pcs->base, pcs->size);
|
||||
|
||||
|
|
@ -1665,6 +1978,12 @@ static int pcs_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct pcs_soc_data pinctrl_single_omap_wkup = {
|
||||
.flags = PCS_QUIRK_SHARED_IRQ,
|
||||
.irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
|
||||
.irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
|
||||
};
|
||||
|
||||
static const struct pcs_soc_data pinctrl_single = {
|
||||
};
|
||||
|
||||
|
|
@ -1673,6 +1992,9 @@ static const struct pcs_soc_data pinconf_single = {
|
|||
};
|
||||
|
||||
static struct of_device_id pcs_of_match[] = {
|
||||
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
|
||||
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
|
||||
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
|
||||
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
|
||||
{ .compatible = "pinconf-single", .data = &pinconf_single },
|
||||
{ },
|
||||
|
|
|
|||
Loading…
Reference in New Issue