powerpc: Fix decrementer setup on 1GHz boards
We noticed that recent kernels didn't boot on our 1GHz Canyonlands 460EX
boards anymore. As it seems, patch 8d165db1
[powerpc: Improve
decrementer accuracy] introduced this problem. The routine div_sc()
overflows with shift = 32 resulting in this incorrect setup:
time_init: decrementer frequency = 1000.000012 MHz
time_init: processor frequency = 1000.000012 MHz
clocksource: timebase mult[400000] shift[22] registered
clockevent: decrementer mult[33] shift[32] cpu[0]
This patch now introduces a local div_dc64() version of this function
so that this overflow doesn't happen anymore.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Detlev Zundel <dzu@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
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@ -903,12 +903,21 @@ static void decrementer_set_mode(enum clock_event_mode mode,
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decrementer_set_next_event(DECREMENTER_MAX, dev);
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}
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static inline uint64_t div_sc64(unsigned long ticks, unsigned long nsec,
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int shift)
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{
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uint64_t tmp = ((uint64_t)ticks) << shift;
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do_div(tmp, nsec);
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return tmp;
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}
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static void __init setup_clockevent_multiplier(unsigned long hz)
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{
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u64 mult, shift = 32;
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while (1) {
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mult = div_sc(hz, NSEC_PER_SEC, shift);
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mult = div_sc64(hz, NSEC_PER_SEC, shift);
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if (mult && (mult >> 32UL) == 0UL)
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break;
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