clk: bcm: rpi: Split pllb clock hooks
The driver only supports the pllb for now and all the clock framework hooks are a mix of the generic firmware interface and the specifics of the pllb. Since we will support more clocks in the future let's split the generic and specific hooks Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/fdc21962fdc7de5c46232f198672d5d5c868ec74.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -102,8 +102,8 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
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}
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static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct raspberrypi_clk_data *data =
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container_of(hw, struct raspberrypi_clk_data, hw);
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@ -116,21 +116,27 @@ static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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if (ret)
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return ret;
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return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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return val;
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}
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static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return raspberrypi_fw_get_rate(hw, parent_rate) *
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RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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}
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static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct raspberrypi_clk_data *data =
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container_of(hw, struct raspberrypi_clk_data, hw);
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struct raspberrypi_clk *rpi = data->rpi;
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u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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u32 _rate = rate;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware, data,
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RPI_FIRMWARE_SET_CLOCK_RATE,
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&new_rate);
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RPI_FIRMWARE_SET_CLOCK_RATE, &_rate);
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if (ret)
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dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
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clk_hw_get_name(hw), ret);
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@ -138,6 +144,14 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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return ret;
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}
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static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
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}
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/*
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* Sadly there is no firmware rate rounding interface. We borrowed it from
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* clk-bcm2835.
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