dmaengine: omap-dma: consolidate setup of CCR
Consolidate the setup of the channel control register. Prepare the basic value in the preparation of the DMA descriptor, and write it into the register upon descriptor execution. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Russell King
parent
2f0d13bdf6
commit
3ed4d18f39
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@ -58,8 +58,7 @@ struct omap_desc {
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int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
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uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
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uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
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uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
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uint32_t ccr; /* CCR value */
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uint16_t cicr; /* CICR value */
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uint32_t csdp; /* CSDP value */
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@ -227,7 +226,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
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{
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struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
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struct omap_desc *d;
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uint32_t val;
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if (!vd) {
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c->desc = NULL;
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@ -239,23 +237,15 @@ static void omap_dma_start_desc(struct omap_chan *c)
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c->desc = d = to_omap_dma_desc(&vd->tx);
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c->sgidx = 0;
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if (d->dir == DMA_DEV_TO_MEM) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 14 | 0x03 << 12);
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val |= OMAP_DMA_AMODE_POST_INC << 14;
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val |= OMAP_DMA_AMODE_CONSTANT << 12;
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(d->ccr, CCR, c->dma_ch);
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if (dma_omap1())
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c->plat->dma_write(d->ccr >> 16, CCR2, c->dma_ch);
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if (d->dir == DMA_DEV_TO_MEM) {
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c->plat->dma_write(d->dev_addr, CSSA, c->dma_ch);
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c->plat->dma_write(0, CSEI, c->dma_ch);
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c->plat->dma_write(d->fi, CSFI, c->dma_ch);
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} else {
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(0x03 << 12 | 0x03 << 14);
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val |= OMAP_DMA_AMODE_CONSTANT << 14;
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val |= OMAP_DMA_AMODE_POST_INC << 12;
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c->plat->dma_write(val, CCR, c->dma_ch);
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c->plat->dma_write(d->dev_addr, CDSA, c->dma_ch);
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c->plat->dma_write(0, CDEI, c->dma_ch);
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c->plat->dma_write(d->fi, CDFI, c->dma_ch);
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@ -263,45 +253,6 @@ static void omap_dma_start_desc(struct omap_chan *c)
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c->plat->dma_write(d->csdp, CSDP, c->dma_ch);
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if (dma_omap1()) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(1 << 5);
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if (d->sync_mode == OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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c->plat->dma_write(val, CCR, c->dma_ch);
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val = c->plat->dma_read(CCR2, c->dma_ch);
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val &= ~(1 << 2);
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if (d->sync_mode == OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 2;
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c->plat->dma_write(val, CCR2, c->dma_ch);
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} else if (c->dma_sig) {
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val = c->plat->dma_read(CCR, c->dma_ch);
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/* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
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val &= ~(1 << 24 | 1 << 23 | 3 << 19 | 1 << 18 | 1 << 5 | 0x1f);
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val |= (c->dma_sig & ~0x1f) << 14;
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val |= c->dma_sig & 0x1f;
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if (d->sync_mode & OMAP_DMA_SYNC_FRAME)
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val |= 1 << 5;
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if (d->sync_mode & OMAP_DMA_SYNC_BLOCK)
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val |= 1 << 18;
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switch (d->sync_type) {
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case OMAP_DMA_DST_SYNC_PREFETCH:/* dest synch */
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val |= 1 << 23; /* Prefetch */
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break;
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case 0:
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break;
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default:
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val |= 1 << 24; /* source synch */
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break;
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}
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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omap_dma_start_sg(c, d, 0);
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}
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@ -540,19 +491,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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struct scatterlist *sgent;
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struct omap_desc *d;
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dma_addr_t dev_addr;
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unsigned i, j = 0, es, en, frame_bytes, sync_type;
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unsigned i, j = 0, es, en, frame_bytes;
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u32 burst;
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if (dir == DMA_DEV_TO_MEM) {
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dev_addr = c->cfg.src_addr;
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dev_width = c->cfg.src_addr_width;
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burst = c->cfg.src_maxburst;
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sync_type = OMAP_DMA_SRC_SYNC;
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} else if (dir == DMA_MEM_TO_DEV) {
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dev_addr = c->cfg.dst_addr;
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dev_width = c->cfg.dst_addr_width;
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burst = c->cfg.dst_maxburst;
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sync_type = OMAP_DMA_DST_SYNC;
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} else {
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dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
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return NULL;
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@ -581,12 +530,28 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->dir = dir;
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d->dev_addr = dev_addr;
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d->es = es;
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d->sync_mode = OMAP_DMA_SYNC_FRAME;
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d->sync_type = sync_type;
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d->ccr = 0;
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
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OMAP_DMA_AMODE_CONSTANT << 12;
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else
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d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
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OMAP_DMA_AMODE_POST_INC << 12;
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d->cicr = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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d->csdp = es;
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if (dma_omap1()) {
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d->ccr |= 1 << 5; /* frame sync */
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if (__dma_omap16xx(od->plat->dma_attr)) {
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d->ccr |= 1 << 10; /* disable 3.0/3.1 compatibility mode */
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/* Duplicate what plat-omap/dma.c does */
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d->ccr |= c->dma_ch + 1;
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} else {
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d->ccr |= c->dma_sig & 0x1f;
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}
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d->cicr |= OMAP1_DMA_TOUT_IRQ;
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if (dir == DMA_DEV_TO_MEM)
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@ -596,6 +561,13 @@ static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
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d->csdp |= OMAP_DMA_PORT_TIPB << 9 |
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OMAP_DMA_PORT_EMIFF << 2;
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} else {
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d->ccr |= (c->dma_sig & ~0x1f) << 14;
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d->ccr |= c->dma_sig & 0x1f;
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d->ccr |= 1 << 5; /* frame sync */
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= 1 << 24; /* source synch */
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d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
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}
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@ -632,19 +604,17 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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enum dma_slave_buswidth dev_width;
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struct omap_desc *d;
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dma_addr_t dev_addr;
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unsigned es, sync_type;
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unsigned es;
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u32 burst;
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if (dir == DMA_DEV_TO_MEM) {
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dev_addr = c->cfg.src_addr;
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dev_width = c->cfg.src_addr_width;
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burst = c->cfg.src_maxburst;
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sync_type = OMAP_DMA_SRC_SYNC;
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} else if (dir == DMA_MEM_TO_DEV) {
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dev_addr = c->cfg.dst_addr;
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dev_width = c->cfg.dst_addr_width;
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burst = c->cfg.dst_maxburst;
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sync_type = OMAP_DMA_DST_SYNC;
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} else {
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dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
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return NULL;
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@ -674,15 +644,21 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->dev_addr = dev_addr;
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d->fi = burst;
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d->es = es;
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if (burst)
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d->sync_mode = OMAP_DMA_SYNC_PACKET;
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else
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d->sync_mode = OMAP_DMA_SYNC_ELEMENT;
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d->sync_type = sync_type;
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d->sg[0].addr = buf_addr;
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d->sg[0].en = period_len / es_bytes[es];
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d->sg[0].fn = buf_len / period_len;
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d->sglen = 1;
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d->ccr = 0;
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if (__dma_omap15xx(od->plat->dma_attr))
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d->ccr = 3 << 8;
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= OMAP_DMA_AMODE_POST_INC << 14 |
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OMAP_DMA_AMODE_CONSTANT << 12;
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else
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d->ccr |= OMAP_DMA_AMODE_CONSTANT << 14 |
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OMAP_DMA_AMODE_POST_INC << 12;
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d->cicr = OMAP_DMA_DROP_IRQ;
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if (flags & DMA_PREP_INTERRUPT)
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d->cicr |= OMAP_DMA_FRAME_IRQ;
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@ -690,6 +666,14 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->csdp = es;
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if (dma_omap1()) {
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if (__dma_omap16xx(od->plat->dma_attr)) {
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d->ccr |= 1 << 10; /* disable 3.0/3.1 compatibility mode */
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/* Duplicate what plat-omap/dma.c does */
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d->ccr |= c->dma_ch + 1;
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} else {
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d->ccr |= c->dma_sig & 0x1f;
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}
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d->cicr |= OMAP1_DMA_TOUT_IRQ;
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if (dir == DMA_DEV_TO_MEM)
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@ -699,23 +683,22 @@ static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
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d->csdp |= OMAP_DMA_PORT_MPUI << 9 |
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OMAP_DMA_PORT_EMIFF << 2;
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} else {
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d->ccr |= (c->dma_sig & ~0x1f) << 14;
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d->ccr |= c->dma_sig & 0x1f;
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if (burst)
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d->ccr |= 1 << 18 | 1 << 5; /* packet */
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if (dir == DMA_DEV_TO_MEM)
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d->ccr |= 1 << 24; /* source synch */
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d->cicr |= OMAP2_DMA_MISALIGNED_ERR_IRQ | OMAP2_DMA_TRANS_ERR_IRQ;
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/* src and dst burst mode 16 */
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d->csdp |= 3 << 14 | 3 << 7;
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}
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if (!c->cyclic) {
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c->cyclic = true;
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if (__dma_omap15xx(od->plat->dma_attr)) {
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uint32_t val;
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val = c->plat->dma_read(CCR, c->dma_ch);
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val |= 3 << 8;
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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}
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c->cyclic = true;
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return vchan_tx_prep(&c->vc, &d->vd, flags);
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}
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@ -759,14 +742,6 @@ static int omap_dma_terminate_all(struct omap_chan *c)
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if (c->cyclic) {
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c->cyclic = false;
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c->paused = false;
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if (__dma_omap15xx(od->plat->dma_attr)) {
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uint32_t val;
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val = c->plat->dma_read(CCR, c->dma_ch);
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val &= ~(3 << 8);
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c->plat->dma_write(val, CCR, c->dma_ch);
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}
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}
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vchan_get_all_descriptors(&c->vc, &head);
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