drm: bridge/dw_hdmi: add dw hdmi i2c bus adapter support
The change adds support of internal HDMI I2C master controller, this subdevice is used by default, if "ddc-i2c-bus" DT property is omitted. The main purpose of this functionality is to support reading EDID from an HDMI monitor on boards, which don't have an I2C bus connected to DDC pins. The current implementation does not support "I2C Master Interface Extended Read Mode" to read data addressed by non-zero segment pointer, this means that if EDID has more than 1 extension blocks, EDID reading operation won't succeed, in my practice all tested HDMI monitors have at maximum one extension block. Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
Vladimir Zapolskiy
Philipp Zabel
parent
9f04a1f2b3
commit
3efc2fa3b7
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@ -19,7 +19,9 @@ Required properties:
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Optional properties
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- reg-io-width: the width of the reg:1,4, default set to 1 if not present
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
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if the property is omitted, a functionally reduced I2C bus
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controller on DW HDMI is probed
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- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
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Example:
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@ -1,14 +1,15 @@
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/*
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* DesignWare High-Definition Multimedia Interface (HDMI) driver
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*
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* Copyright (C) 2013-2015 Mentor Graphics Inc.
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* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Designware High-Definition Multimedia Interface (HDMI) driver
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*
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* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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@ -101,6 +102,17 @@ struct hdmi_data_info {
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struct hdmi_vmode video_mode;
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};
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struct dw_hdmi_i2c {
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struct i2c_adapter adap;
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struct mutex lock; /* used to serialize data transfers */
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struct completion cmp;
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u8 stat;
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u8 slave_reg;
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bool is_regaddr;
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};
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struct dw_hdmi {
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struct drm_connector connector;
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struct drm_encoder *encoder;
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@ -111,6 +123,7 @@ struct dw_hdmi {
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struct device *dev;
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struct clk *isfr_clk;
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struct clk *iahb_clk;
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struct dw_hdmi_i2c *i2c;
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struct hdmi_data_info hdmi_data;
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const struct dw_hdmi_plat_data *plat_data;
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@ -198,6 +211,201 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
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hdmi_modb(hdmi, data << shift, mask, reg);
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}
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static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
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{
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/* Software reset */
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hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
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/* Set Standard Mode speed (determined to be 100KHz on iMX6) */
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hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
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/* Set done, not acknowledged and arbitration interrupt polarities */
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hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
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hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
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HDMI_I2CM_CTLINT);
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/* Clear DONE and ERROR interrupts */
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hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
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HDMI_IH_I2CM_STAT0);
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/* Mute DONE and ERROR interrupts */
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hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
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HDMI_IH_MUTE_I2CM_STAT0);
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}
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static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
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unsigned char *buf, unsigned int length)
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{
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struct dw_hdmi_i2c *i2c = hdmi->i2c;
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int stat;
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if (!i2c->is_regaddr) {
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dev_dbg(hdmi->dev, "set read register address to 0\n");
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i2c->slave_reg = 0x00;
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i2c->is_regaddr = true;
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}
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while (length--) {
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reinit_completion(&i2c->cmp);
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hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
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hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
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HDMI_I2CM_OPERATION);
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stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
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if (!stat)
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return -EAGAIN;
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/* Check for error condition on the bus */
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if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
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return -EIO;
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*buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
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}
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return 0;
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}
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static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
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unsigned char *buf, unsigned int length)
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{
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struct dw_hdmi_i2c *i2c = hdmi->i2c;
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int stat;
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if (!i2c->is_regaddr) {
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/* Use the first write byte as register address */
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i2c->slave_reg = buf[0];
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length--;
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buf++;
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i2c->is_regaddr = true;
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}
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while (length--) {
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reinit_completion(&i2c->cmp);
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hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
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hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
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hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
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HDMI_I2CM_OPERATION);
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stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
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if (!stat)
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return -EAGAIN;
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/* Check for error condition on the bus */
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if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
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return -EIO;
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}
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return 0;
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}
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static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
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struct i2c_msg *msgs, int num)
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{
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struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
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struct dw_hdmi_i2c *i2c = hdmi->i2c;
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u8 addr = msgs[0].addr;
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int i, ret = 0;
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dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
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for (i = 0; i < num; i++) {
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if (msgs[i].addr != addr) {
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dev_warn(hdmi->dev,
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"unsupported transfer, changed slave address\n");
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return -EOPNOTSUPP;
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}
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if (msgs[i].len == 0) {
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dev_dbg(hdmi->dev,
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"unsupported transfer %d/%d, no data\n",
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i + 1, num);
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return -EOPNOTSUPP;
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}
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}
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mutex_lock(&i2c->lock);
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/* Unmute DONE and ERROR interrupts */
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hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
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/* Set slave device address taken from the first I2C message */
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hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
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/* Set slave device register address on transfer */
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i2c->is_regaddr = false;
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for (i = 0; i < num; i++) {
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dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
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i + 1, num, msgs[i].len, msgs[i].flags);
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if (msgs[i].flags & I2C_M_RD)
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ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, msgs[i].len);
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else
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ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, msgs[i].len);
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if (ret < 0)
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break;
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}
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if (!ret)
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ret = num;
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/* Mute DONE and ERROR interrupts */
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hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
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HDMI_IH_MUTE_I2CM_STAT0);
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mutex_unlock(&i2c->lock);
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return ret;
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}
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static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static const struct i2c_algorithm dw_hdmi_algorithm = {
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.master_xfer = dw_hdmi_i2c_xfer,
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.functionality = dw_hdmi_i2c_func,
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};
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static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
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{
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struct i2c_adapter *adap;
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struct dw_hdmi_i2c *i2c;
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int ret;
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i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return ERR_PTR(-ENOMEM);
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mutex_init(&i2c->lock);
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init_completion(&i2c->cmp);
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adap = &i2c->adap;
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adap->class = I2C_CLASS_DDC;
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adap->owner = THIS_MODULE;
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adap->dev.parent = hdmi->dev;
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adap->algo = &dw_hdmi_algorithm;
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strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
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i2c_set_adapdata(adap, hdmi);
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ret = i2c_add_adapter(adap);
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if (ret) {
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dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
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devm_kfree(hdmi->dev, i2c);
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return ERR_PTR(ret);
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}
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hdmi->i2c = i2c;
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dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
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return adap;
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}
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static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
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unsigned int n)
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{
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@ -1517,16 +1725,40 @@ static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
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.mode_set = dw_hdmi_bridge_mode_set,
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};
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static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
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{
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struct dw_hdmi_i2c *i2c = hdmi->i2c;
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unsigned int stat;
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stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
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if (!stat)
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return IRQ_NONE;
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hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
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i2c->stat = stat;
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complete(&i2c->cmp);
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return IRQ_HANDLED;
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}
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static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
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{
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struct dw_hdmi *hdmi = dev_id;
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u8 intr_stat;
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irqreturn_t ret = IRQ_NONE;
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if (hdmi->i2c)
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ret = dw_hdmi_i2c_irq(hdmi);
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intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
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if (intr_stat)
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if (intr_stat) {
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hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
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return IRQ_WAKE_THREAD;
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}
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return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
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return ret;
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}
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static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
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@ -1751,6 +1983,13 @@ int dw_hdmi_bind(struct device *dev, struct device *master,
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*/
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hdmi_init_clk_regenerator(hdmi);
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/* If DDC bus is not specified, try to register HDMI I2C bus */
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if (!hdmi->ddc) {
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hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
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if (IS_ERR(hdmi->ddc))
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hdmi->ddc = NULL;
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}
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/*
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* Configure registers related to HDMI interrupt
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* generation before registering IRQ.
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@ -1791,11 +2030,20 @@ int dw_hdmi_bind(struct device *dev, struct device *master,
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hdmi->audio = platform_device_register_full(&pdevinfo);
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}
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/* Reset HDMI DDC I2C master controller and mute I2CM interrupts */
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if (hdmi->i2c)
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dw_hdmi_i2c_init(hdmi);
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dev_set_drvdata(dev, hdmi);
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return 0;
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err_iahb:
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if (hdmi->i2c) {
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i2c_del_adapter(&hdmi->i2c->adap);
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hdmi->ddc = NULL;
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}
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clk_disable_unprepare(hdmi->iahb_clk);
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err_isfr:
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clk_disable_unprepare(hdmi->isfr_clk);
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@ -1821,13 +2069,18 @@ void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
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clk_disable_unprepare(hdmi->iahb_clk);
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clk_disable_unprepare(hdmi->isfr_clk);
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i2c_put_adapter(hdmi->ddc);
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if (hdmi->i2c)
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i2c_del_adapter(&hdmi->i2c->adap);
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else
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i2c_put_adapter(hdmi->ddc);
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}
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EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
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MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
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MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
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MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
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MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
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MODULE_DESCRIPTION("DW HDMI transmitter driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:dw-hdmi");
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@ -566,6 +566,10 @@ enum {
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HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
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HDMI_IH_PHY_STAT0_HPD = 0x1,
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/* IH_I2CM_STAT0 and IH_MUTE_I2CM_STAT0 field values */
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HDMI_IH_I2CM_STAT0_DONE = 0x2,
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HDMI_IH_I2CM_STAT0_ERROR = 0x1,
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/* IH_MUTE_I2CMPHY_STAT0 field values */
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HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
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HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
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@ -1032,6 +1036,21 @@ enum {
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HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
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HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
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HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
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/* I2CM_OPERATION field values */
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HDMI_I2CM_OPERATION_WRITE = 0x10,
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HDMI_I2CM_OPERATION_READ_EXT = 0x2,
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HDMI_I2CM_OPERATION_READ = 0x1,
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/* I2CM_INT field values */
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HDMI_I2CM_INT_DONE_POL = 0x8,
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HDMI_I2CM_INT_DONE_MASK = 0x4,
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/* I2CM_CTLINT field values */
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HDMI_I2CM_CTLINT_NAC_POL = 0x80,
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HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
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HDMI_I2CM_CTLINT_ARB_POL = 0x8,
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HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
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};
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#endif /* __DW_HDMI_H__ */
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