tg3: Convert PHY_ADDR => TG3_PHY_MII_ADDR
This patch renames the PHY_ADDR preprocessor definition. The following patch will identify a new member on the MDIO bus, so we want this preprocessor definition to be a little more descriptive. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
f40386c845
commit
3f0e3ad723
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@ -937,7 +937,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp)
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u32 val;
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struct phy_device *phydev;
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
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case TG3_PHY_ID_BCM50610:
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val = MAC_PHYCFG2_50610_LED_MODES;
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@ -1031,7 +1031,7 @@ static void tg3_mdio_start(struct tg3 *tp)
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if (is_serdes)
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tp->phy_addr += 7;
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} else
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tp->phy_addr = PHY_ADDR;
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tp->phy_addr = TG3_PHY_MII_ADDR;
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if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
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@ -1062,7 +1062,7 @@ static int tg3_mdio_init(struct tg3 *tp)
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tp->mdio_bus->read = &tg3_mdio_read;
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tp->mdio_bus->write = &tg3_mdio_write;
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tp->mdio_bus->reset = &tg3_mdio_reset;
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tp->mdio_bus->phy_mask = ~(1 << PHY_ADDR);
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tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
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tp->mdio_bus->irq = &tp->mdio_irq[0];
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for (i = 0; i < PHY_MAX_ADDR; i++)
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@ -1084,7 +1084,7 @@ static int tg3_mdio_init(struct tg3 *tp)
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return i;
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}
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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if (!phydev || !phydev->drv) {
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printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
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@ -1311,7 +1311,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
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u32 old_tx_mode = tp->tx_mode;
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
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autoneg = tp->mdio_bus->phy_map[PHY_ADDR]->autoneg;
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autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
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else
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autoneg = tp->link_config.autoneg;
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@ -1348,7 +1348,7 @@ static void tg3_adjust_link(struct net_device *dev)
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u8 oldflowctrl, linkmesg = 0;
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u32 mac_mode, lcl_adv, rmt_adv;
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struct tg3 *tp = netdev_priv(dev);
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struct phy_device *phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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spin_lock_bh(&tp->lock);
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@ -1434,7 +1434,7 @@ static int tg3_phy_init(struct tg3 *tp)
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/* Bring the PHY back to a known state. */
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tg3_bmcr_reset(tp);
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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/* Attach the MAC to the PHY. */
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phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
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@ -1461,7 +1461,7 @@ static int tg3_phy_init(struct tg3 *tp)
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SUPPORTED_Asym_Pause);
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break;
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default:
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phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
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phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
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return -EINVAL;
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}
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@ -1479,7 +1479,7 @@ static void tg3_phy_start(struct tg3 *tp)
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return;
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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if (tp->link_config.phy_is_low_power) {
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tp->link_config.phy_is_low_power = 0;
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@ -1499,13 +1499,13 @@ static void tg3_phy_stop(struct tg3 *tp)
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return;
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phy_stop(tp->mdio_bus->phy_map[PHY_ADDR]);
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phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
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}
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static void tg3_phy_fini(struct tg3 *tp)
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{
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if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
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phy_disconnect(tp->mdio_bus->phy_map[PHY_ADDR]);
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phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
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tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
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}
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}
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@ -2474,7 +2474,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
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struct phy_device *phydev;
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u32 phyid, advertising;
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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tp->link_config.phy_is_low_power = 1;
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@ -9243,9 +9243,11 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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struct tg3 *tp = netdev_priv(dev);
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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struct phy_device *phydev;
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return -EAGAIN;
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return phy_ethtool_gset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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return phy_ethtool_gset(phydev, cmd);
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}
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cmd->supported = (SUPPORTED_Autoneg);
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@ -9284,9 +9286,11 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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struct tg3 *tp = netdev_priv(dev);
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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struct phy_device *phydev;
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return -EAGAIN;
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return phy_ethtool_sset(tp->mdio_bus->phy_map[PHY_ADDR], cmd);
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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return phy_ethtool_sset(phydev, cmd);
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}
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if (cmd->autoneg != AUTONEG_ENABLE &&
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@ -9469,7 +9473,7 @@ static int tg3_nway_reset(struct net_device *dev)
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return -EAGAIN;
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r = phy_start_aneg(tp->mdio_bus->phy_map[PHY_ADDR]);
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r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
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} else {
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u32 bmcr;
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@ -9588,7 +9592,7 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
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u32 newadv;
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struct phy_device *phydev;
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phydev = tp->mdio_bus->phy_map[PHY_ADDR];
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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if (epause->rx_pause) {
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if (epause->tx_pause)
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@ -10568,9 +10572,11 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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int err;
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if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
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struct phy_device *phydev;
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if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
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return -EAGAIN;
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return phy_mii_ioctl(tp->mdio_bus->phy_map[PHY_ADDR], data, cmd);
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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return phy_mii_ioctl(phydev, data, cmd);
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}
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switch(cmd) {
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@ -14135,13 +14141,14 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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tg3_bus_string(tp, str),
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dev->dev_addr);
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if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
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if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
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struct phy_device *phydev;
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phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
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printk(KERN_INFO
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"%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
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tp->dev->name,
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tp->mdio_bus->phy_map[PHY_ADDR]->drv->name,
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dev_name(&tp->mdio_bus->phy_map[PHY_ADDR]->dev));
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else
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tp->dev->name, phydev->drv->name,
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dev_name(&phydev->dev));
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} else
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printk(KERN_INFO
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"%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
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tp->dev->name, tg3_phy_string(tp),
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@ -1954,7 +1954,7 @@
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#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
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/* Currently this is fixed. */
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#define PHY_ADDR 0x01
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#define TG3_PHY_MII_ADDR 0x01
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/* Tigon3 specific PHY MII registers. */
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#define TG3_BMCR_SPEED1000 0x0040
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