iommu/arm-smmu-v3: Share process page tables
With Shared Virtual Addressing (SVA), we need to mirror CPU TTBR, TCR, MAIR and ASIDs in SMMU contexts. Each SMMU has a single ASID space split into two sets, shared and private. Shared ASIDs correspond to those obtained from the arch ASID allocator, and private ASIDs are used for "classic" map/unmap DMA. A possible conflict happens when trying to use a shared ASID that has already been allocated for private use by the SMMU driver. This will be addressed in a later patch by replacing the private ASID. At the moment we return -EBUSY. Each mm_struct shared with the SMMU will have a single context descriptor. Add a refcount to keep track of this. It will be protected by the global SVA lock. Introduce a new arm-smmu-v3-sva.c file and the CONFIG_ARM_SMMU_V3_SVA option to let users opt in SVA support. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200918101852.582559-9-jean-philippe@linaro.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -308,6 +308,16 @@ config ARM_SMMU_V3
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Say Y here if your system includes an IOMMU device implementing
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the ARM SMMUv3 architecture.
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config ARM_SMMU_V3_SVA
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bool "Shared Virtual Addressing support for the ARM SMMUv3"
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depends on ARM_SMMU_V3
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help
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Support for sharing process address spaces with devices using the
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SMMUv3.
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Say Y here if your system supports SVA extensions such as PCIe PASID
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and PRI.
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config S390_IOMMU
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def_bool y if S390 && PCI
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depends on S390 && PCI
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@ -1,2 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_SMMU_V3) += arm-smmu-v3.o
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obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
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arm_smmu_v3-objs-y += arm-smmu-v3.o
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arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
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arm_smmu_v3-objs := $(arm_smmu_v3-objs-y)
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123
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
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123
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
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@ -0,0 +1,123 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Implementation of the IOMMU SVA API for the ARM SMMUv3
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*/
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#include <linux/mm.h>
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#include <linux/mmu_context.h>
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#include <linux/slab.h>
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#include "arm-smmu-v3.h"
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#include "../../io-pgtable-arm.h"
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static struct arm_smmu_ctx_desc *
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arm_smmu_share_asid(struct mm_struct *mm, u16 asid)
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{
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struct arm_smmu_ctx_desc *cd;
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cd = xa_load(&arm_smmu_asid_xa, asid);
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if (!cd)
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return NULL;
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if (cd->mm) {
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if (WARN_ON(cd->mm != mm))
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return ERR_PTR(-EINVAL);
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/* All devices bound to this mm use the same cd struct. */
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refcount_inc(&cd->refs);
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return cd;
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}
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/* Ouch, ASID is already in use for a private cd. */
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return ERR_PTR(-EBUSY);
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}
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__maybe_unused
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static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
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{
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u16 asid;
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int err = 0;
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u64 tcr, par, reg;
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struct arm_smmu_ctx_desc *cd;
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struct arm_smmu_ctx_desc *ret = NULL;
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asid = arm64_mm_context_get(mm);
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if (!asid)
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return ERR_PTR(-ESRCH);
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cd = kzalloc(sizeof(*cd), GFP_KERNEL);
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if (!cd) {
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err = -ENOMEM;
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goto out_put_context;
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}
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refcount_set(&cd->refs, 1);
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mutex_lock(&arm_smmu_asid_lock);
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ret = arm_smmu_share_asid(mm, asid);
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if (ret) {
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mutex_unlock(&arm_smmu_asid_lock);
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goto out_free_cd;
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}
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err = xa_insert(&arm_smmu_asid_xa, asid, cd, GFP_KERNEL);
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mutex_unlock(&arm_smmu_asid_lock);
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if (err)
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goto out_free_asid;
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tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - vabits_actual) |
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FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, ARM_LPAE_TCR_RGN_WBWA) |
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FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, ARM_LPAE_TCR_RGN_WBWA) |
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FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS) |
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CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;
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switch (PAGE_SIZE) {
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case SZ_4K:
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tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K);
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break;
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case SZ_16K:
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tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K);
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break;
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case SZ_64K:
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tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K);
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break;
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default:
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WARN_ON(1);
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err = -EINVAL;
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goto out_free_asid;
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}
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reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
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par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
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tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
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cd->ttbr = virt_to_phys(mm->pgd);
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cd->tcr = tcr;
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/*
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* MAIR value is pretty much constant and global, so we can just get it
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* from the current CPU register
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*/
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cd->mair = read_sysreg(mair_el1);
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cd->asid = asid;
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cd->mm = mm;
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return cd;
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out_free_asid:
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arm_smmu_free_asid(cd);
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out_free_cd:
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kfree(cd);
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out_put_context:
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arm64_mm_context_put(mm);
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return err < 0 ? ERR_PTR(err) : ret;
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}
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__maybe_unused
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static void arm_smmu_free_shared_cd(struct arm_smmu_ctx_desc *cd)
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{
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if (arm_smmu_free_asid(cd)) {
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/* Unpin ASID */
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arm64_mm_context_put(cd->mm);
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kfree(cd);
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}
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}
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@ -73,7 +73,8 @@ struct arm_smmu_option_prop {
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const char *prop;
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};
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static DEFINE_XARRAY_ALLOC1(asid_xa);
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DEFINE_XARRAY_ALLOC1(arm_smmu_asid_xa);
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DEFINE_MUTEX(arm_smmu_asid_lock);
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static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
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@ -1013,7 +1014,8 @@ static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain,
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#ifdef __BIG_ENDIAN
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CTXDESC_CD_0_ENDI |
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#endif
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CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET |
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CTXDESC_CD_0_R | CTXDESC_CD_0_A |
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(cd->mm ? 0 : CTXDESC_CD_0_ASET) |
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CTXDESC_CD_0_AA64 |
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FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) |
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CTXDESC_CD_0_V;
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@ -1117,12 +1119,20 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain)
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cdcfg->cdtab = NULL;
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}
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static void arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)
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bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)
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{
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if (!cd->asid)
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return;
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bool free;
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struct arm_smmu_ctx_desc *old_cd;
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xa_erase(&asid_xa, cd->asid);
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if (!cd->asid)
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return false;
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free = refcount_dec_and_test(&cd->refs);
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if (free) {
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old_cd = xa_erase(&arm_smmu_asid_xa, cd->asid);
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WARN_ON(old_cd != cd);
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}
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return free;
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}
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/* Stream table manipulation functions */
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if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
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struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
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/* Prevent SVA from touching the CD while we're freeing it */
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mutex_lock(&arm_smmu_asid_lock);
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if (cfg->cdcfg.cdtab)
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arm_smmu_free_cd_tables(smmu_domain);
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arm_smmu_free_asid(&cfg->cd);
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mutex_unlock(&arm_smmu_asid_lock);
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} else {
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struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;
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if (cfg->vmid)
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struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;
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typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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ret = xa_alloc(&asid_xa, &asid, &cfg->cd,
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refcount_set(&cfg->cd.refs, 1);
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/* Prevent SVA from modifying the ASID until it is written to the CD */
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mutex_lock(&arm_smmu_asid_lock);
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ret = xa_alloc(&arm_smmu_asid_xa, &asid, &cfg->cd,
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XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
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if (ret)
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return ret;
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goto out_unlock;
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cfg->s1cdmax = master->ssid_bits;
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if (ret)
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goto out_free_cd_tables;
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mutex_unlock(&arm_smmu_asid_lock);
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return 0;
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out_free_cd_tables:
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arm_smmu_free_cd_tables(smmu_domain);
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out_free_asid:
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arm_smmu_free_asid(&cfg->cd);
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out_unlock:
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mutex_unlock(&arm_smmu_asid_lock);
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return ret;
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}
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@ -540,6 +540,9 @@ struct arm_smmu_ctx_desc {
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u64 ttbr;
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u64 tcr;
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u64 mair;
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refcount_t refs;
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struct mm_struct *mm;
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};
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struct arm_smmu_l1_ctx_desc {
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spinlock_t devices_lock;
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};
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extern struct xarray arm_smmu_asid_xa;
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extern struct mutex arm_smmu_asid_lock;
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bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd);
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#endif /* _ARM_SMMU_V3_H */
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