drm/gm100/device: recognise GM107
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
c68c29c04c
commit
3f204647cd
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@ -211,6 +211,7 @@ nouveau-y += core/engine/device/nv40.o
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nouveau-y += core/engine/device/nv50.o
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nouveau-y += core/engine/device/nvc0.o
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nouveau-y += core/engine/device/nve0.o
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nouveau-y += core/engine/device/gm100.o
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nouveau-y += core/engine/disp/base.o
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nouveau-y += core/engine/disp/nv04.o
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nouveau-y += core/engine/disp/nv50.o
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@ -185,6 +185,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
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case 0x0e0:
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case 0x0f0:
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case 0x100: device->card_type = NV_E0; break;
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case 0x110: device->card_type = GM100; break;
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default:
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break;
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}
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@ -208,6 +209,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
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case NV_C0:
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case NV_D0: ret = nvc0_identify(device); break;
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case NV_E0: ret = nve0_identify(device); break;
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case GM100: ret = gm100_identify(device); break;
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default:
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ret = -EINVAL;
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break;
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108
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
Normal file
108
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
Normal file
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@ -0,0 +1,108 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <subdev/bios.h>
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#include <subdev/bus.h>
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#include <subdev/gpio.h>
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#include <subdev/i2c.h>
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#include <subdev/clock.h>
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#include <subdev/therm.h>
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#include <subdev/mxm.h>
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#include <subdev/devinit.h>
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#include <subdev/mc.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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#include <subdev/ltcg.h>
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#include <subdev/ibus.h>
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#include <subdev/instmem.h>
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#include <subdev/vm.h>
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#include <subdev/bar.h>
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#include <subdev/pwr.h>
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#include <subdev/volt.h>
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#include <engine/device.h>
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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#include <engine/software.h>
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#include <engine/graph.h>
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#include <engine/disp.h>
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#include <engine/copy.h>
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#include <engine/bsp.h>
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#include <engine/vp.h>
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#include <engine/ppp.h>
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#include <engine/perfmon.h>
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int
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gm100_identify(struct nouveau_device *device)
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{
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switch (device->chipset) {
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case 0x117:
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device->cname = "GM107";
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
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device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
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device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
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device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
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#if 0
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device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
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#endif
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
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device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
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device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
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device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
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device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
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device->oclass[NVDEV_SUBDEV_LTCG ] = gm107_ltcg_oclass;
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device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
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device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
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#if 0
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device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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#endif
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
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device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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#if 0
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device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass;
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#endif
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device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
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#if 0
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
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#endif
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device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
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#if 0
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device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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#endif
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break;
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default:
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nv_fatal(device, "unknown Maxwell chipset\n");
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return -EINVAL;
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}
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return 0;
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}
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@ -85,6 +85,7 @@ struct nouveau_device {
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NV_C0 = 0xc0,
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NV_D0 = 0xd0,
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NV_E0 = 0xe0,
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GM100 = 0x110,
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} card_type;
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u32 chipset;
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u32 crystal;
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@ -17,6 +17,7 @@ int nv40_identify(struct nouveau_device *);
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int nv50_identify(struct nouveau_device *);
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int nvc0_identify(struct nouveau_device *);
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int nve0_identify(struct nouveau_device *);
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int gm100_identify(struct nouveau_device *);
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struct nouveau_device *nouveau_device_find(u64 name);
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