ntb: remove Intel Atom NTB driver support
Removing dead code since this is not being used. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>hifive-unleashed-5.1
Dave Jiang
Jon Mason
parent
0ed08f829b
commit
3f7756728e
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@ -74,12 +74,6 @@ MODULE_AUTHOR("Intel Corporation");
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#define bar0_off(base, bar) ((base) + ((bar) << 2))
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#define bar2_off(base, bar) bar0_off(base, (bar) - 2)
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static const struct intel_ntb_reg atom_reg;
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static const struct intel_ntb_alt_reg atom_pri_reg;
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static const struct intel_ntb_alt_reg atom_sec_reg;
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static const struct intel_ntb_alt_reg atom_b2b_reg;
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static const struct intel_ntb_xlat_reg atom_pri_xlat;
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static const struct intel_ntb_xlat_reg atom_sec_xlat;
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static const struct intel_ntb_reg xeon_reg;
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static const struct intel_ntb_alt_reg xeon_pri_reg;
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static const struct intel_ntb_alt_reg xeon_sec_reg;
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@ -184,15 +178,6 @@ static inline void _iowrite64(u64 val, void __iomem *mmio)
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#endif
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#endif
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static inline int pdev_is_atom(struct pci_dev *pdev)
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{
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_NTB_B2B_BWD:
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return 1;
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}
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return 0;
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}
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static inline int pdev_is_xeon(struct pci_dev *pdev)
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{
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switch (pdev->device) {
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@ -1006,8 +991,7 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
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{
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struct intel_ntb_dev *ndev = filp->private_data;
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if (pdev_is_xeon(ndev->ntb.pdev) ||
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pdev_is_atom(ndev->ntb.pdev))
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if (pdev_is_xeon(ndev->ntb.pdev))
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return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
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else if (pdev_is_skx_xeon(ndev->ntb.pdev))
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return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
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@ -1439,242 +1423,6 @@ static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx,
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ndev->peer_reg->spad);
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}
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/* ATOM */
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static u64 atom_db_ioread(void __iomem *mmio)
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{
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return ioread64(mmio);
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}
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static void atom_db_iowrite(u64 bits, void __iomem *mmio)
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{
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iowrite64(bits, mmio);
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}
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static int atom_poll_link(struct intel_ntb_dev *ndev)
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{
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u32 ntb_ctl;
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ntb_ctl = ioread32(ndev->self_mmio + ATOM_NTBCNTL_OFFSET);
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if (ntb_ctl == ndev->ntb_ctl)
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return 0;
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ndev->ntb_ctl = ntb_ctl;
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ndev->lnk_sta = ioread32(ndev->self_mmio + ATOM_LINK_STATUS_OFFSET);
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return 1;
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}
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static int atom_link_is_up(struct intel_ntb_dev *ndev)
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{
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return ATOM_NTB_CTL_ACTIVE(ndev->ntb_ctl);
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}
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static int atom_link_is_err(struct intel_ntb_dev *ndev)
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{
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if (ioread32(ndev->self_mmio + ATOM_LTSSMSTATEJMP_OFFSET)
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& ATOM_LTSSMSTATEJMP_FORCEDETECT)
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return 1;
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if (ioread32(ndev->self_mmio + ATOM_IBSTERRRCRVSTS0_OFFSET)
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& ATOM_IBIST_ERR_OFLOW)
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return 1;
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return 0;
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}
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static inline enum ntb_topo atom_ppd_topo(struct intel_ntb_dev *ndev, u32 ppd)
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{
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struct device *dev = &ndev->ntb.pdev->dev;
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switch (ppd & ATOM_PPD_TOPO_MASK) {
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case ATOM_PPD_TOPO_B2B_USD:
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dev_dbg(dev, "PPD %d B2B USD\n", ppd);
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return NTB_TOPO_B2B_USD;
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case ATOM_PPD_TOPO_B2B_DSD:
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dev_dbg(dev, "PPD %d B2B DSD\n", ppd);
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return NTB_TOPO_B2B_DSD;
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case ATOM_PPD_TOPO_PRI_USD:
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case ATOM_PPD_TOPO_PRI_DSD: /* accept bogus PRI_DSD */
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case ATOM_PPD_TOPO_SEC_USD:
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case ATOM_PPD_TOPO_SEC_DSD: /* accept bogus SEC_DSD */
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dev_dbg(dev, "PPD %d non B2B disabled\n", ppd);
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return NTB_TOPO_NONE;
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}
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dev_dbg(dev, "PPD %d invalid\n", ppd);
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return NTB_TOPO_NONE;
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}
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static void atom_link_hb(struct work_struct *work)
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{
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struct intel_ntb_dev *ndev = hb_ndev(work);
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struct device *dev = &ndev->ntb.pdev->dev;
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unsigned long poll_ts;
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void __iomem *mmio;
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u32 status32;
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poll_ts = ndev->last_ts + ATOM_LINK_HB_TIMEOUT;
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/* Delay polling the link status if an interrupt was received,
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* unless the cached link status says the link is down.
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*/
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if (time_after(poll_ts, jiffies) && atom_link_is_up(ndev)) {
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schedule_delayed_work(&ndev->hb_timer, poll_ts - jiffies);
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return;
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}
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if (atom_poll_link(ndev))
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ntb_link_event(&ndev->ntb);
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if (atom_link_is_up(ndev) || !atom_link_is_err(ndev)) {
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schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
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return;
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}
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/* Link is down with error: recover the link! */
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mmio = ndev->self_mmio;
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/* Driver resets the NTB ModPhy lanes - magic! */
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iowrite8(0xe0, mmio + ATOM_MODPHY_PCSREG6);
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iowrite8(0x40, mmio + ATOM_MODPHY_PCSREG4);
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iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG4);
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iowrite8(0x60, mmio + ATOM_MODPHY_PCSREG6);
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/* Driver waits 100ms to allow the NTB ModPhy to settle */
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msleep(100);
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/* Clear AER Errors, write to clear */
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status32 = ioread32(mmio + ATOM_ERRCORSTS_OFFSET);
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dev_dbg(dev, "ERRCORSTS = %x\n", status32);
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status32 &= PCI_ERR_COR_REP_ROLL;
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iowrite32(status32, mmio + ATOM_ERRCORSTS_OFFSET);
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/* Clear unexpected electrical idle event in LTSSM, write to clear */
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status32 = ioread32(mmio + ATOM_LTSSMERRSTS0_OFFSET);
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dev_dbg(dev, "LTSSMERRSTS0 = %x\n", status32);
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status32 |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI;
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iowrite32(status32, mmio + ATOM_LTSSMERRSTS0_OFFSET);
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/* Clear DeSkew Buffer error, write to clear */
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status32 = ioread32(mmio + ATOM_DESKEWSTS_OFFSET);
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dev_dbg(dev, "DESKEWSTS = %x\n", status32);
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status32 |= ATOM_DESKEWSTS_DBERR;
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iowrite32(status32, mmio + ATOM_DESKEWSTS_OFFSET);
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status32 = ioread32(mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
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dev_dbg(dev, "IBSTERRRCRVSTS0 = %x\n", status32);
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status32 &= ATOM_IBIST_ERR_OFLOW;
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iowrite32(status32, mmio + ATOM_IBSTERRRCRVSTS0_OFFSET);
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/* Releases the NTB state machine to allow the link to retrain */
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status32 = ioread32(mmio + ATOM_LTSSMSTATEJMP_OFFSET);
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dev_dbg(dev, "LTSSMSTATEJMP = %x\n", status32);
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status32 &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT;
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iowrite32(status32, mmio + ATOM_LTSSMSTATEJMP_OFFSET);
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/* There is a potential race between the 2 NTB devices recovering at the
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* same time. If the times are the same, the link will not recover and
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* the driver will be stuck in this loop forever. Add a random interval
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* to the recovery time to prevent this race.
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*/
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schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_RECOVERY_TIME
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+ prandom_u32() % ATOM_LINK_RECOVERY_TIME);
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}
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static int atom_init_isr(struct intel_ntb_dev *ndev)
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{
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int rc;
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rc = ndev_init_isr(ndev, 1, ATOM_DB_MSIX_VECTOR_COUNT,
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ATOM_DB_MSIX_VECTOR_SHIFT, ATOM_DB_TOTAL_SHIFT);
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if (rc)
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return rc;
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/* ATOM doesn't have link status interrupt, poll on that platform */
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ndev->last_ts = jiffies;
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INIT_DELAYED_WORK(&ndev->hb_timer, atom_link_hb);
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schedule_delayed_work(&ndev->hb_timer, ATOM_LINK_HB_TIMEOUT);
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return 0;
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}
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static void atom_deinit_isr(struct intel_ntb_dev *ndev)
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{
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cancel_delayed_work_sync(&ndev->hb_timer);
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ndev_deinit_isr(ndev);
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}
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static int atom_init_ntb(struct intel_ntb_dev *ndev)
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{
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ndev->mw_count = ATOM_MW_COUNT;
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ndev->spad_count = ATOM_SPAD_COUNT;
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ndev->db_count = ATOM_DB_COUNT;
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switch (ndev->ntb.topo) {
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case NTB_TOPO_B2B_USD:
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case NTB_TOPO_B2B_DSD:
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ndev->self_reg = &atom_pri_reg;
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ndev->peer_reg = &atom_b2b_reg;
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ndev->xlat_reg = &atom_sec_xlat;
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/* Enable Bus Master and Memory Space on the secondary side */
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iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
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ndev->self_mmio + ATOM_SPCICMD_OFFSET);
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break;
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default:
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return -EINVAL;
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}
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ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
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return 0;
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}
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static int atom_init_dev(struct intel_ntb_dev *ndev)
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{
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u32 ppd;
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int rc;
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rc = pci_read_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET, &ppd);
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if (rc)
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return -EIO;
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ndev->ntb.topo = atom_ppd_topo(ndev, ppd);
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if (ndev->ntb.topo == NTB_TOPO_NONE)
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return -EINVAL;
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rc = atom_init_ntb(ndev);
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if (rc)
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return rc;
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rc = atom_init_isr(ndev);
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if (rc)
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return rc;
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if (ndev->ntb.topo != NTB_TOPO_SEC) {
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/* Initiate PCI-E link training */
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rc = pci_write_config_dword(ndev->ntb.pdev, ATOM_PPD_OFFSET,
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ppd | ATOM_PPD_INIT_LINK);
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if (rc)
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return rc;
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}
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return 0;
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}
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static void atom_deinit_dev(struct intel_ntb_dev *ndev)
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{
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atom_deinit_isr(ndev);
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}
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/* Skylake Xeon NTB */
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static int skx_poll_link(struct intel_ntb_dev *ndev)
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@ -2658,24 +2406,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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node = dev_to_node(&pdev->dev);
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if (pdev_is_atom(pdev)) {
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ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
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if (!ndev) {
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rc = -ENOMEM;
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goto err_ndev;
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}
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ndev_init_struct(ndev, pdev);
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rc = intel_ntb_init_pci(ndev, pdev);
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if (rc)
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goto err_init_pci;
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rc = atom_init_dev(ndev);
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if (rc)
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goto err_init_dev;
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} else if (pdev_is_xeon(pdev)) {
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if (pdev_is_xeon(pdev)) {
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ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
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if (!ndev) {
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rc = -ENOMEM;
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@ -2731,9 +2462,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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err_register:
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ndev_deinit_debugfs(ndev);
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if (pdev_is_atom(pdev))
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atom_deinit_dev(ndev);
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else if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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xeon_deinit_dev(ndev);
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err_init_dev:
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intel_ntb_deinit_pci(ndev);
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@ -2749,41 +2478,12 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
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ntb_unregister_device(&ndev->ntb);
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ndev_deinit_debugfs(ndev);
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if (pdev_is_atom(pdev))
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atom_deinit_dev(ndev);
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else if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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xeon_deinit_dev(ndev);
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intel_ntb_deinit_pci(ndev);
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kfree(ndev);
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}
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static const struct intel_ntb_reg atom_reg = {
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.poll_link = atom_poll_link,
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.link_is_up = atom_link_is_up,
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.db_ioread = atom_db_ioread,
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.db_iowrite = atom_db_iowrite,
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.db_size = sizeof(u64),
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.ntb_ctl = ATOM_NTBCNTL_OFFSET,
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.mw_bar = {2, 4},
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};
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static const struct intel_ntb_alt_reg atom_pri_reg = {
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.db_bell = ATOM_PDOORBELL_OFFSET,
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.db_mask = ATOM_PDBMSK_OFFSET,
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.spad = ATOM_SPAD_OFFSET,
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};
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static const struct intel_ntb_alt_reg atom_b2b_reg = {
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.db_bell = ATOM_B2B_DOORBELL_OFFSET,
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.spad = ATOM_B2B_SPAD_OFFSET,
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};
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static const struct intel_ntb_xlat_reg atom_sec_xlat = {
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/* FIXME : .bar0_base = ATOM_SBAR0BASE_OFFSET, */
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/* FIXME : .bar2_limit = ATOM_SBAR2LMT_OFFSET, */
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.bar2_xlat = ATOM_SBAR2XLAT_OFFSET,
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};
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static const struct intel_ntb_reg xeon_reg = {
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.poll_link = xeon_poll_link,
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.link_is_up = xeon_link_is_up,
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@ -2940,7 +2640,6 @@ static const struct file_operations intel_ntb_debugfs_info = {
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};
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static const struct pci_device_id intel_ntb_pci_tbl[] = {
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{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_BWD)},
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{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_JSF)},
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{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_SNB)},
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{PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_NTB_B2B_IVT)},
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@ -66,7 +66,6 @@
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BWD 0x0C4E
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#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
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#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
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#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
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@ -196,63 +195,6 @@
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#define SKX_DB_TOTAL_SHIFT 33
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#define SKX_SPAD_COUNT 16
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/* Intel Atom hardware */
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#define ATOM_SBAR2XLAT_OFFSET 0x0008
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#define ATOM_PDOORBELL_OFFSET 0x0020
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#define ATOM_PDBMSK_OFFSET 0x0028
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#define ATOM_NTBCNTL_OFFSET 0x0060
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#define ATOM_SPAD_OFFSET 0x0080
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#define ATOM_PPD_OFFSET 0x00d4
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#define ATOM_PBAR2XLAT_OFFSET 0x8008
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#define ATOM_B2B_DOORBELL_OFFSET 0x8020
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#define ATOM_B2B_SPAD_OFFSET 0x8080
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#define ATOM_SPCICMD_OFFSET 0xb004
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#define ATOM_LINK_STATUS_OFFSET 0xb052
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#define ATOM_ERRCORSTS_OFFSET 0xb110
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#define ATOM_IP_BASE 0xc000
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#define ATOM_DESKEWSTS_OFFSET (ATOM_IP_BASE + 0x3024)
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#define ATOM_LTSSMERRSTS0_OFFSET (ATOM_IP_BASE + 0x3180)
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#define ATOM_LTSSMSTATEJMP_OFFSET (ATOM_IP_BASE + 0x3040)
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#define ATOM_IBSTERRRCRVSTS0_OFFSET (ATOM_IP_BASE + 0x3324)
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#define ATOM_MODPHY_PCSREG4 0x1c004
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#define ATOM_MODPHY_PCSREG6 0x1c006
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#define ATOM_PPD_INIT_LINK 0x0008
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#define ATOM_PPD_CONN_MASK 0x0300
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#define ATOM_PPD_CONN_TRANSPARENT 0x0000
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#define ATOM_PPD_CONN_B2B 0x0100
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#define ATOM_PPD_CONN_RP 0x0200
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#define ATOM_PPD_DEV_MASK 0x1000
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#define ATOM_PPD_DEV_USD 0x0000
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#define ATOM_PPD_DEV_DSD 0x1000
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#define ATOM_PPD_TOPO_MASK (ATOM_PPD_CONN_MASK | ATOM_PPD_DEV_MASK)
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#define ATOM_PPD_TOPO_PRI_USD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_PRI_DSD (ATOM_PPD_CONN_TRANSPARENT | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_SEC_USD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_SEC_DSD (ATOM_PPD_CONN_RP | ATOM_PPD_DEV_DSD)
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#define ATOM_PPD_TOPO_B2B_USD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_USD)
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#define ATOM_PPD_TOPO_B2B_DSD (ATOM_PPD_CONN_B2B | ATOM_PPD_DEV_DSD)
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#define ATOM_MW_COUNT 2
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#define ATOM_DB_COUNT 34
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#define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
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#define ATOM_DB_MSIX_VECTOR_COUNT 34
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#define ATOM_DB_MSIX_VECTOR_SHIFT 1
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#define ATOM_DB_TOTAL_SHIFT 34
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#define ATOM_SPAD_COUNT 16
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#define ATOM_NTB_CTL_DOWN_BIT BIT(16)
|
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#define ATOM_NTB_CTL_ACTIVE(x) !(x & ATOM_NTB_CTL_DOWN_BIT)
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#define ATOM_DESKEWSTS_DBERR BIT(15)
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#define ATOM_LTSSMERRSTS0_UNEXPECTEDEI BIT(20)
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#define ATOM_LTSSMSTATEJMP_FORCEDETECT BIT(2)
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#define ATOM_IBIST_ERR_OFLOW 0x7FFF7FFF
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||||
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||||
#define ATOM_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
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#define ATOM_LINK_RECOVERY_TIME msecs_to_jiffies(500)
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|
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/* Ntb control and link status */
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|
||||
#define NTB_CTL_CFG_LOCK BIT(0)
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||||
|
|
|
|||
Loading…
Reference in New Issue