ARM: dts: mvebu: Add device tree for 98DX3236 SoCs
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs with integrated CPUs. They are similar to the Armada XP SoCs but have different I/O interfaces. [gregory.clement@free-electrons.com: fix topic] Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>hifive-unleashed-5.1
Chris Packham
Gregory CLEMENT
parent
a3fe1d5dce
commit
3f81df559f
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Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
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----------------------------------------------------------------------
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Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
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shall have the following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx3236"
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In addition, boards using the Marvell 98DX3336 SoC shall have the
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following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx3336"
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In addition, boards using the Marvell 98DX4251 SoC shall have the
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following property:
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Required root node property:
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compatible: must contain "marvell,armadaxp-98dx4251"
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@ -0,0 +1,50 @@
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Marvell Prestera Switch Chip bindings
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-------------------------------------
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Required properties:
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- compatible: one of the following
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"marvell,prestera-98dx3236",
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"marvell,prestera-98dx3336",
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"marvell,prestera-98dx4251",
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- reg: address and length of the register set for the device.
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- interrupts: interrupt for the device
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Optional properties:
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- dfx: phandle reference to the "DFX Server" node
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Example:
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switch {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
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packet-processor@0 {
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compatible = "marvell,prestera-98dx3236";
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reg = <0 0x4000000>;
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interrupts = <33>, <34>, <35>;
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dfx = <&dfx>;
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};
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};
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DFX Server bindings
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-------------------
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Required properties:
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- compatible: must be "marvell,dfx-server"
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- reg: address and length of the register set for the device.
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Example:
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dfx-registers {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
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dfx: dfx@0 {
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compatible = "marvell,dfx-server";
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reg = <0 0x100000>;
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};
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};
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@ -0,0 +1,254 @@
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/*
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* Device Tree Include file for Marvell 98dx3236 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Contains definitions specific to the 98dx3236 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-xp.dtsi"
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/ {
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model = "Marvell 98DX3236 SoC";
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compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,98dx3236-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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clock-latency = <1000000>;
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};
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
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MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
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/*
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* 98DX3236 has 1 x1 PCIe unit Gen2.0
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*/
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pciec: pcie-controller@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */>;
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pcie1: pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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};
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internal-regs {
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,mv98dx3236-core-clock";
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};
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cpuclk: clock-complex@18700 {
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compatible = "marvell,mv98dx3236-cpu-clock";
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};
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corediv-clock@18740 {
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status = "disabled";
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};
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xor@60900 {
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status = "disabled";
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};
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crypto@90000 {
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status = "disabled";
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};
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xor@f0900 {
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status = "disabled";
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};
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xor@f0800 {
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compatible = "marvell,orion-xor";
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reg = <0xf0800 0x100
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0xf0a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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/* does not exist */
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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status = "disabled";
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};
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gpio2: gpio@18180 { /* rework some properties */
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <1>; /* only gpio #32 */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <87>;
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};
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nand: nand@d0000 {
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clocks = <&dfx_coredivclk 0>;
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};
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};
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dfxr: dfx-registers@ac000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
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dfx_coredivclk: corediv-clock@f8268 {
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compatible = "marvell,mv98dx3236-corediv-clock";
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reg = <0xf8268 0xc>;
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#clock-cells = <1>;
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clocks = <&mainpll>;
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clock-output-names = "nand";
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};
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dfx: dfx@0 {
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compatible = "marvell,dfx-server";
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reg = <0 0x100000>;
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};
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};
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switch: switch@a8000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
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pp0: packet-processor@0 {
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compatible = "marvell,prestera-98dx3236";
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reg = <0 0x4000000>;
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interrupts = <33>, <34>, <35>;
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dfx = <&dfx>;
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};
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};
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};
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};
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&pinctrl {
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compatible = "marvell,98dx3236-pinctrl";
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spi0_pins: spi0-pins {
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marvell,pins = "mpp0", "mpp1",
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"mpp2", "mpp3";
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marvell,function = "spi0";
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};
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};
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&sdio {
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status = "disabled";
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};
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&crypto_sram0 {
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status = "disabled";
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};
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&crypto_sram1 {
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status = "disabled";
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};
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@ -0,0 +1,76 @@
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/*
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* Device Tree Include file for Marvell 98dx3336 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
|
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
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* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
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||||
*
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* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following
|
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* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
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* Contains definitions specific to the 98dx3236 SoC that are not
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* common to all Armada XP SoCs.
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*/
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#include "armada-xp-98dx3236.dtsi"
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/ {
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model = "Marvell 98DX3336 SoC";
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compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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cpus {
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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clock-latency = <1000000>;
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};
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};
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soc {
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internal-regs {
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resume@20980 {
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compatible = "marvell,98dx3336-resume-ctrl";
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reg = <0x20980 0x10>;
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};
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};
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};
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};
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&pp0 {
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compatible = "marvell,prestera-98dx3336";
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};
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@ -0,0 +1,90 @@
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/*
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* Device Tree Include file for Marvell 98dx4521 family SoC
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*
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* Copyright (C) 2016 Allied Telesis Labs
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*
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* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the 98dx4521 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
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|
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#include "armada-xp-98dx3236.dtsi"
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/ {
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model = "Marvell 98DX4251 SoC";
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compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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cpus {
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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clock-latency = <1000000>;
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};
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};
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soc {
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internal-regs {
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resume@20980 {
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compatible = "marvell,98dx3336-resume-ctrl";
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reg = <0x20980 0x10>;
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};
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};
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};
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};
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&sdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,98dx4251-pinctrl";
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
};
|
||||
|
||||
&pp0 {
|
||||
compatible = "marvell,prestera-98dx4251";
|
||||
};
|
||||
Loading…
Reference in New Issue