drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set
The pipe and plane _are_ disabled when we call this. So replace it all with the corresponding assert (as self-documenting code) and rip out all the lore. Checking for a disabled plane would require us to export those macros from intel_display.c, but if the pipe is off the plane isn't working either. So this single check is good enough. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1026,7 +1026,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
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const struct video_levels *video_levels;
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const struct color_conversion *color_conversion;
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bool burst_ena;
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int pipe = intel_crtc->pipe;
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int xpos = 0x0, ypos = 0x0;
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unsigned int xsize, ysize;
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if (!tv_mode)
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return; /* can't happen (mode_prepare prevents this) */
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@ -1110,24 +1111,8 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
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I915_WRITE(TV_CLR_LEVEL,
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((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
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(video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
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{
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int pipeconf_reg = PIPECONF(pipe);
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int dspcntr_reg = DSPCNTR(intel_crtc->plane);
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int pipeconf = I915_READ(pipeconf_reg);
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int dspcntr = I915_READ(dspcntr_reg);
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int xpos = 0x0, ypos = 0x0;
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unsigned int xsize, ysize;
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/* Pipe must be off here */
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I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
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intel_flush_primary_plane(dev_priv, intel_crtc->plane);
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/* Wait for vblank for the disable to take effect */
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if (IS_GEN2(dev))
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
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/* Wait for vblank for the disable to take effect. */
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intel_wait_for_pipe_off(dev, intel_crtc->pipe);
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assert_pipe_disabled(dev_priv, intel_crtc->pipe);
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/* Filter ctl must be set before TV_WIN_SIZE */
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I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
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@ -1146,11 +1131,6 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
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I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
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I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
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I915_WRITE(pipeconf_reg, pipeconf);
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I915_WRITE(dspcntr_reg, dspcntr);
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intel_flush_primary_plane(dev_priv, intel_crtc->plane);
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}
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j = 0;
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for (i = 0; i < 60; i++)
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I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
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