net: dsa: b53: Implement software reset for 58xx devices
Implement the correct software reset sequence for 58xx devices by
setting all 3 reset bits and polling for the SW_RST bit to clear itself
without a given timeout. We cannot use is58xx() here because that would
also include the 7445/7278 Starfighter 2 which have their own driver
doing the reset earlier on due to the HW specific integration.
Fixes: 991a36bb46
("net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switch")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
a424f0de61
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3fb22b0534
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@ -608,7 +608,8 @@ static void b53_switch_reset_gpio(struct b53_device *dev)
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static int b53_switch_reset(struct b53_device *dev)
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{
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u8 mgmt;
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unsigned int timeout = 1000;
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u8 mgmt, reg;
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b53_switch_reset_gpio(dev);
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@ -617,6 +618,28 @@ static int b53_switch_reset(struct b53_device *dev)
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b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
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}
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/* This is specific to 58xx devices here, do not use is58xx() which
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* covers the larger Starfigther 2 family, including 7445/7278 which
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* still use this driver as a library and need to perform the reset
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* earlier.
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*/
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if (dev->chip_id == BCM58XX_DEVICE_ID) {
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b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
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reg |= SW_RST | EN_SW_RST | EN_CH_RST;
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b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
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do {
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b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
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if (!(reg & SW_RST))
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break;
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usleep_range(1000, 2000);
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} while (timeout-- > 0);
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if (timeout == 0)
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return -ETIMEDOUT;
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}
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b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
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if (!(mgmt & SM_SW_FWD_EN)) {
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@ -143,6 +143,7 @@
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/* Software reset register (8 bit) */
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#define B53_SOFTRESET 0x79
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#define SW_RST BIT(7)
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#define EN_CH_RST BIT(6)
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#define EN_SW_RST BIT(4)
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/* Fast Aging Control register (8 bit) */
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