drm/i915: Simplify i915_reg_read_ioctl
Convert to use the freshly available made INTEL_GEN_MASK for easier grepping and improve function readability and clarify the UABI documentation. No functional changes. v2: - Lift GEM_BUG_ONs and use is_power_of_2 (Chris) - Retain -EINVAL on bad flags behavior (Chris) v3: - Extract flags with 'entry->size - 1' (Chris) v4: - Add GEM_BUG_ON on for flags vs entry offset (Chris) v5: - Use 'u16' to match 'dev_priv' (Ville) v6: - Fix checkpatch.pl errors Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170913115255.13851-2-joonas.lahtinen@linux.intel.com
This commit is contained in:
Joonas Lahtinen
parent
fe52e597fd
commit
3fd3a6ffe2
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@ -1292,72 +1292,65 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv)
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intel_uncore_forcewake_reset(dev_priv, false);
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}
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#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)
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static const struct register_whitelist {
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i915_reg_t offset_ldw, offset_udw;
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uint32_t size;
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/* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
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uint32_t gen_bitmask;
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} whitelist[] = {
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{ .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
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.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
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.size = 8, .gen_bitmask = GEN_RANGE(4, 10) },
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};
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static const struct reg_whitelist {
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i915_reg_t offset_ldw;
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i915_reg_t offset_udw;
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u16 gen_mask;
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u8 size;
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} reg_read_whitelist[] = { {
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.offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE),
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.offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE),
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.gen_mask = INTEL_GEN_MASK(4, 10),
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.size = 8
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} };
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int i915_reg_read_ioctl(struct drm_device *dev,
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void *data, struct drm_file *file)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct drm_i915_reg_read *reg = data;
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struct register_whitelist const *entry = whitelist;
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unsigned size;
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i915_reg_t offset_ldw, offset_udw;
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int i, ret = 0;
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struct reg_whitelist const *entry;
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unsigned int flags;
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int remain;
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int ret = 0;
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for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
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if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&
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(INTEL_INFO(dev_priv)->gen_mask & entry->gen_bitmask))
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entry = reg_read_whitelist;
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remain = ARRAY_SIZE(reg_read_whitelist);
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while (remain) {
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u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw);
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GEM_BUG_ON(!is_power_of_2(entry->size));
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GEM_BUG_ON(entry->size > 8);
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GEM_BUG_ON(entry_offset & (entry->size - 1));
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if (INTEL_INFO(dev_priv)->gen_mask & entry->gen_mask &&
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entry_offset == (reg->offset & -entry->size))
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break;
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entry++;
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remain--;
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}
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if (i == ARRAY_SIZE(whitelist))
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if (!remain)
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return -EINVAL;
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/* We use the low bits to encode extra flags as the register should
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* be naturally aligned (and those that are not so aligned merely
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* limit the available flags for that register).
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*/
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offset_ldw = entry->offset_ldw;
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offset_udw = entry->offset_udw;
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size = entry->size;
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size |= reg->offset ^ i915_mmio_reg_offset(offset_ldw);
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flags = reg->offset & (entry->size - 1);
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intel_runtime_pm_get(dev_priv);
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switch (size) {
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case 8 | 1:
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reg->val = I915_READ64_2x32(offset_ldw, offset_udw);
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break;
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case 8:
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reg->val = I915_READ64(offset_ldw);
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break;
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case 4:
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reg->val = I915_READ(offset_ldw);
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break;
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case 2:
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reg->val = I915_READ16(offset_ldw);
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break;
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case 1:
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reg->val = I915_READ8(offset_ldw);
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break;
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default:
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if (entry->size == 8 && flags == I915_REG_READ_8B_WA)
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reg->val = I915_READ64_2x32(entry->offset_ldw,
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entry->offset_udw);
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else if (entry->size == 8 && flags == 0)
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reg->val = I915_READ64(entry->offset_ldw);
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else if (entry->size == 4 && flags == 0)
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reg->val = I915_READ(entry->offset_ldw);
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else if (entry->size == 2 && flags == 0)
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reg->val = I915_READ16(entry->offset_ldw);
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else if (entry->size == 1 && flags == 0)
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reg->val = I915_READ8(entry->offset_ldw);
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else
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ret = -EINVAL;
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goto out;
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}
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out:
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intel_runtime_pm_put(dev_priv);
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return ret;
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}
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@ -1308,14 +1308,16 @@ struct drm_i915_reg_read {
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* be specified
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*/
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__u64 offset;
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#define I915_REG_READ_8B_WA BIT(0)
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__u64 val; /* Return value */
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};
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/* Known registers:
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*
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* Render engine timestamp - 0x2358 + 64bit - gen7+
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* - Note this register returns an invalid value if using the default
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* single instruction 8byte read, in order to workaround that use
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* offset (0x2538 | 1) instead.
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* single instruction 8byte read, in order to workaround that pass
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* flag I915_REG_READ_8B_WA in offset field.
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*
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*/
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