staging: tidspbridge: remove RET_OK RET_FAIL
RET_OK is 0 and RET_FAIL is a -1, replace these custom returns with a standard errno Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Felipe Contreras <felipe.contreras@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Nishanth Menon
Greg Kroah-Hartman
parent
7124cb1711
commit
4018e39651
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@ -1506,8 +1506,7 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
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}
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paddr += HW_PAGE_SIZE4KB;
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}
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if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)
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== RET_FAIL) {
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if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
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status = -EPERM;
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goto EXIT_LOOP;
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}
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@ -1524,9 +1523,8 @@ static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
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/*
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* Clear the L1 PTE pointing to the L2 PT
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*/
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if (hw_mmu_pte_clear(l1_base_va, va_curr_orig,
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HW_MMU_COARSE_PAGE_SIZE) ==
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RET_OK)
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if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
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HW_MMU_COARSE_PAGE_SIZE))
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status = 0;
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else {
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status = -EPERM;
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@ -1571,7 +1569,7 @@ skip_coarse_page:
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}
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paddr += HW_PAGE_SIZE4KB;
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}
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if (hw_mmu_pte_clear(l1_base_va, va_curr, pte_size) == RET_OK) {
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if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
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status = 0;
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rem_bytes -= pte_size;
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va_curr += pte_size;
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@ -22,6 +22,7 @@
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#include <hw_defs.h>
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#include <hw_mmu.h>
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#include <linux/types.h>
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#include <linux/err.h>
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#define MMU_BASE_VAL_MASK 0xFC00
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#define MMU_PAGE_MAX 3
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@ -59,7 +60,7 @@ enum hw_mmu_page_size_t {
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* RETURNS:
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*
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* Type : hw_status
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* Description : RET_OK -- No errors occured
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* Description : 0 -- No errors occured
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* RET_BAD_NULL_PARAM -- A Pointer
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* Paramater was set to NULL
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*
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@ -102,7 +103,7 @@ static hw_status mmu_flush_entry(const void __iomem *base_address);
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* RETURNS:
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*
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* Type : hw_status
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* Description : RET_OK -- No errors occured
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* Description : 0 -- No errors occured
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* RET_BAD_NULL_PARAM -- A Pointer Paramater
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* was set to NULL
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* RET_PARAM_OUT_OF_RANGE -- Input Parameter out
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@ -147,7 +148,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
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* RETURNS:
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*
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* Type : hw_status
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* Description : RET_OK -- No errors occured
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* Description : 0 -- No errors occured
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* RET_BAD_NULL_PARAM -- A Pointer Paramater
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* was set to NULL
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* RET_PARAM_OUT_OF_RANGE -- Input Parameter
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@ -167,7 +168,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
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hw_status hw_mmu_enable(const void __iomem *base_address)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_SET);
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@ -176,7 +177,7 @@ hw_status hw_mmu_enable(const void __iomem *base_address)
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hw_status hw_mmu_disable(const void __iomem *base_address)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, HW_CLEAR);
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@ -186,7 +187,7 @@ hw_status hw_mmu_disable(const void __iomem *base_address)
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hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
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u32 num_locked_entries)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, num_locked_entries);
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@ -196,7 +197,7 @@ hw_status hw_mmu_num_locked_set(const void __iomem *base_address,
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hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
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u32 victim_entry_num)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, victim_entry_num);
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@ -205,7 +206,7 @@ hw_status hw_mmu_victim_num_set(const void __iomem *base_address,
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hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, irq_mask);
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@ -214,7 +215,7 @@ hw_status hw_mmu_event_ack(const void __iomem *base_address, u32 irq_mask)
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hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 irq_reg;
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irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
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@ -226,7 +227,7 @@ hw_status hw_mmu_event_disable(const void __iomem *base_address, u32 irq_mask)
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hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 irq_reg;
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irq_reg = MMUMMU_IRQENABLE_READ_REGISTER32(base_address);
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@ -238,7 +239,7 @@ hw_status hw_mmu_event_enable(const void __iomem *base_address, u32 irq_mask)
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hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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*irq_mask = MMUMMU_IRQSTATUS_READ_REGISTER32(base_address);
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@ -247,7 +248,7 @@ hw_status hw_mmu_event_status(const void __iomem *base_address, u32 *irq_mask)
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hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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/*Check the input Parameters */
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CHECK_INPUT_PARAM(base_address, 0, RET_BAD_NULL_PARAM,
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@ -261,7 +262,7 @@ hw_status hw_mmu_fault_addr_read(const void __iomem *base_address, u32 *addr)
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hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 load_ttb;
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/*Check the input Parameters */
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@ -277,7 +278,7 @@ hw_status hw_mmu_ttb_set(const void __iomem *base_address, u32 ttb_phys_addr)
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hw_status hw_mmu_twl_enable(const void __iomem *base_address)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_SET);
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@ -286,7 +287,7 @@ hw_status hw_mmu_twl_enable(const void __iomem *base_address)
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hw_status hw_mmu_twl_disable(const void __iomem *base_address)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, HW_CLEAR);
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@ -296,7 +297,7 @@ hw_status hw_mmu_twl_disable(const void __iomem *base_address)
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hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
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u32 page_sz)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 virtual_addr_tag;
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enum hw_mmu_page_size_t pg_size_bits;
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@ -318,7 +319,7 @@ hw_status hw_mmu_tlb_flush(const void __iomem *base_address, u32 virtual_addr,
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break;
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default:
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return RET_FAIL;
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return -EINVAL;
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}
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/* Generate the 20-bit tag from virtual address */
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@ -339,7 +340,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address,
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struct hw_mmu_map_attrs_t *map_attrs,
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s8 preserved_bit, s8 valid_bit)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 lock_reg;
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u32 virtual_addr_tag;
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enum hw_mmu_page_size_t mmu_pg_size;
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@ -371,7 +372,7 @@ hw_status hw_mmu_tlb_add(const void __iomem *base_address,
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break;
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default:
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return RET_FAIL;
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return -EINVAL;
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}
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lock_reg = MMUMMU_LOCK_READ_REGISTER32(base_address);
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@ -406,7 +407,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
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u32 virtual_addr,
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u32 page_sz, struct hw_mmu_map_attrs_t *map_attrs)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 pte_addr, pte_val;
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s32 num_entries = 1;
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@ -466,7 +467,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
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break;
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default:
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return RET_FAIL;
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return -EINVAL;
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}
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while (--num_entries >= 0)
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@ -477,7 +478,7 @@ hw_status hw_mmu_pte_set(const u32 pg_tbl_va,
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hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 pte_addr;
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s32 num_entries = 1;
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@ -510,7 +511,7 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
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break;
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default:
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return RET_FAIL;
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return -EINVAL;
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}
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while (--num_entries >= 0)
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@ -522,7 +523,7 @@ hw_status hw_mmu_pte_clear(const u32 pg_tbl_va, u32 virtual_addr, u32 page_size)
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/* mmu_flush_entry */
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static hw_status mmu_flush_entry(const void __iomem *base_address)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 flush_entry_data = 0x1;
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/*Check the input Parameters */
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@ -542,7 +543,7 @@ static hw_status mmu_set_cam_entry(const void __iomem *base_address,
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const u32 valid_bit,
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const u32 virtual_addr_tag)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 mmu_cam_reg;
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/*Check the input Parameters */
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@ -566,7 +567,7 @@ static hw_status mmu_set_ram_entry(const void __iomem *base_address,
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enum hw_element_size_t element_size,
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enum hw_mmu_mixed_size_t mixed_size)
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{
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hw_status status = RET_OK;
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hw_status status = 0;
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u32 mmu_ram_reg;
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/*Check the input Parameters */
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