drm/radeon: Only flush HDP cache from idle ioctl if BO is in VRAM
The HDP cache only applies to CPU access to VRAM. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -358,15 +358,17 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
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struct drm_gem_object *gobj;
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struct radeon_bo *robj;
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int r;
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uint32_t cur_placement = 0;
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gobj = drm_gem_object_lookup(dev, filp, args->handle);
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if (gobj == NULL) {
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return -ENOENT;
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}
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robj = gem_to_radeon_bo(gobj);
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r = radeon_bo_wait(robj, NULL, false);
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r = radeon_bo_wait(robj, &cur_placement, false);
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/* Flush HDP cache via MMIO if necessary */
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if (rdev->asic->mmio_hdp_flush)
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if (rdev->asic->mmio_hdp_flush &&
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radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
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robj->rdev->asic->mmio_hdp_flush(rdev);
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drm_gem_object_unreference_unlocked(gobj);
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r = radeon_gem_handle_lockup(rdev, r);
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