drm/i915: Make intel_pipe_has_type() and some callers take intel_crtc
For consistency, since that's the rule followed for internal functions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>hifive-unleashed-5.1
Ander Conselvan de Oliveira
Daniel Vetter
parent
c7653199c0
commit
409ee761fd
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@ -406,22 +406,22 @@ static void vlv_clock(int refclk, intel_clock_t *clock)
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/**
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* Returns whether any output on the specified pipe is of the specified type
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*/
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static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
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static bool intel_pipe_has_type(struct intel_crtc *crtc, int type)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct intel_encoder *encoder;
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for_each_encoder_on_crtc(dev, crtc, encoder)
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for_each_encoder_on_crtc(dev, &crtc->base, encoder)
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if (encoder->type == type)
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return true;
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return false;
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}
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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
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int refclk)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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const intel_limit_t *limit;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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@ -442,9 +442,9 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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return limit;
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}
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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
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static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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const intel_limit_t *limit;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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@ -463,9 +463,9 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
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return limit;
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}
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static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
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static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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const intel_limit_t *limit;
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if (HAS_PCH_SPLIT(dev))
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@ -584,7 +584,7 @@ i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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intel_clock_t clock;
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int err = target;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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* For LVDS just rely on its current settings for dual-channel.
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* We haven't figured out how to reliably set up different
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@ -645,7 +645,7 @@ pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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intel_clock_t clock;
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int err = target;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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* For LVDS just rely on its current settings for dual-channel.
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* We haven't figured out how to reliably set up different
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@ -708,7 +708,7 @@ g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
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int err_most = (target >> 8) + (target >> 9);
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found = false;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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if (intel_is_dual_link_lvds(dev))
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clock.p2 = limit->p2.p2_fast;
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else
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@ -1567,7 +1567,7 @@ static int intel_num_dvo_pipes(struct drm_device *dev)
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for_each_intel_crtc(dev, crtc)
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count += crtc->active &&
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
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return count;
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}
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@ -1646,7 +1646,7 @@ static void i9xx_disable_pll(struct intel_crtc *crtc)
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/* Disable DVO 2x clock on both PLLs if necessary */
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if (IS_I830(dev) &&
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
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intel_num_dvo_pipes(dev) == 1) {
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I915_WRITE(DPLL(PIPE_B),
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I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
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@ -1884,7 +1884,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
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val &= ~TRANS_INTERLACE_MASK;
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
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if (HAS_PCH_IBX(dev_priv->dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
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intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
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val |= TRANS_LEGACY_INTERLACED_ILK;
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else
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val |= TRANS_INTERLACED;
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@ -2007,7 +2007,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
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* need the check.
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*/
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if (!HAS_PCH_SPLIT(dev_priv->dev))
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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@ -2846,8 +2846,8 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
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((adjusted_mode->crtc_hdisplay - 1) << 16) |
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(adjusted_mode->crtc_vdisplay - 1));
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if (!crtc->config.pch_pfit.enabled &&
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(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))) {
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(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
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I915_WRITE(PF_CTL(crtc->pipe), 0);
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I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
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I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
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@ -3755,8 +3755,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
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(intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_EDP))) {
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u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
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reg = TRANS_DP_CTL(pipe);
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temp = I915_READ(reg);
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@ -4033,7 +4033,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
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return;
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if (!HAS_PCH_SPLIT(dev_priv->dev)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
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assert_dsi_pll_enabled(dev_priv);
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else
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assert_pll_enabled(dev_priv, pipe);
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@ -4834,7 +4834,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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if (intel_crtc->active)
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return;
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is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
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is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
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if (!is_dsi) {
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if (IS_CHERRYVIEW(dev))
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@ -5028,7 +5028,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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if (encoder->post_disable)
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encoder->post_disable(encoder);
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if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
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if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
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if (IS_CHERRYVIEW(dev))
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chv_disable_pll(dev_priv, pipe);
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else if (IS_VALLEYVIEW(dev))
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@ -5411,7 +5411,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
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* - LVDS dual channel mode
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* - Double wide pipe
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*/
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if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
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pipe_config->pipe_src_w &= ~1;
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@ -5599,9 +5599,9 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
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&& !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
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}
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static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
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static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int refclk;
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@ -5649,7 +5649,7 @@ static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
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crtc->config.dpll_hw_state.fp0 = fp;
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crtc->lowfreq_avail = false;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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reduced_clock && i915.powersave) {
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crtc->config.dpll_hw_state.fp1 = fp2;
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crtc->lowfreq_avail = true;
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@ -5818,16 +5818,16 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
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/* Set HBR and RBR LPF coefficients */
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if (crtc->config.port_clock == 162000 ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
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intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
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0x009f0003);
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else
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
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0x00d0000f);
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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/* Use SSC source */
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if (pipe == PIPE_A)
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
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@ -5847,8 +5847,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc)
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coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
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coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
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coreclk |= 0x01000000;
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vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
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@ -5918,7 +5918,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc)
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(2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
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/* Loop filter */
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refclk = i9xx_get_refclk(&crtc->base, 0);
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refclk = i9xx_get_refclk(crtc, 0);
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loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
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2 << DPIO_CHV_GAIN_CTRL_SHIFT;
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if (refclk == 100000)
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@ -5950,12 +5950,12 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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i9xx_update_pll_dividers(crtc, reduced_clock);
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is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
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is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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@ -5968,7 +5968,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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if (is_sdvo)
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dpll |= DPLL_SDVO_HIGH_SPEED;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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dpll |= DPLL_SDVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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@ -5998,7 +5998,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
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if (crtc->config.sdvo_tv_clock)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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@ -6027,7 +6027,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock->p1 == 2)
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@ -6038,10 +6038,10 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
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dpll |= PLL_P2_DIVIDE_BY_4;
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}
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if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
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if (!IS_I830(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
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dpll |= DPLL_DVO_2X_MODE;
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if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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@ -6072,7 +6072,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
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crtc_vtotal -= 1;
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crtc_vblank_end -= 1;
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if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
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vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
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else
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vsyncshift = adjusted_mode->crtc_hsync_start -
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@ -6230,7 +6230,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
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if (INTEL_INFO(dev)->gen < 4 ||
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intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
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intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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else
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pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
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@ -6274,7 +6274,7 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
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return 0;
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if (!crtc->config.clock_set) {
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refclk = i9xx_get_refclk(&crtc->base, num_connectors);
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refclk = i9xx_get_refclk(crtc, num_connectors);
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/*
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* Returns a set of divisors for the desired target clock with
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@ -6282,7 +6282,7 @@ static int i9xx_crtc_mode_set(struct intel_crtc *crtc,
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* the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
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* 2) / p1 / p2.
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*/
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limit = intel_limit(&crtc->base, refclk);
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limit = intel_limit(crtc, refclk);
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ok = dev_priv->display.find_dpll(limit, crtc,
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crtc->config.port_clock,
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refclk, NULL, &clock);
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@ -7114,7 +7114,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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const intel_limit_t *limit;
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bool ret, is_lvds = false;
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is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
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is_lvds = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_LVDS);
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refclk = ironlake_get_refclk(crtc);
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@ -7123,7 +7123,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
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* refclk, or FALSE. The returned values represent the clock equation:
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* reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
|
||||
*/
|
||||
limit = intel_limit(crtc, refclk);
|
||||
limit = intel_limit(intel_crtc, refclk);
|
||||
ret = dev_priv->display.find_dpll(limit, intel_crtc,
|
||||
intel_crtc->config.port_clock,
|
||||
refclk, NULL, clock);
|
||||
|
|
@ -7259,7 +7259,7 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc,
|
|||
bool is_lvds = false;
|
||||
struct intel_shared_dpll *pll;
|
||||
|
||||
is_lvds = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS);
|
||||
is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
|
||||
|
||||
WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
|
||||
"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
|
||||
|
|
@ -8049,6 +8049,7 @@ static void haswell_write_eld(struct drm_connector *connector,
|
|||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
uint8_t *eld = connector->eld;
|
||||
uint32_t eldv;
|
||||
uint32_t i;
|
||||
|
|
@ -8089,7 +8090,7 @@ static void haswell_write_eld(struct drm_connector *connector,
|
|||
|
||||
eldv = AUDIO_ELD_VALID_A << (pipe * 4);
|
||||
|
||||
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
|
||||
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
|
||||
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
|
||||
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
|
||||
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
|
||||
|
|
@ -8132,6 +8133,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
|
|||
struct drm_display_mode *mode)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
uint8_t *eld = connector->eld;
|
||||
uint32_t eldv;
|
||||
uint32_t i;
|
||||
|
|
@ -8185,7 +8187,7 @@ static void ironlake_write_eld(struct drm_connector *connector,
|
|||
eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
|
||||
}
|
||||
|
||||
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
|
||||
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) {
|
||||
DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
|
||||
eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
|
||||
I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
|
||||
|
|
@ -10880,7 +10882,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
|
|||
|
||||
crtc->scanline_offset = vtotal - 1;
|
||||
} else if (HAS_DDI(dev) &&
|
||||
intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
|
||||
intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
|
||||
crtc->scanline_offset = 2;
|
||||
} else
|
||||
crtc->scanline_offset = 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue