redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

ARM: OMAP2+: McBSP: Correct CLKR/FSR clock source mux configuration

Browse source 
On OMAP2/3 McBSP1 port has 6 pin setup, while on OMAP4 the port is McBSP4.
Implement the CLKR/FSR clock mux selection for OMAP4, and make sure that
we add the correct callback for the correct port across supported OMAP
versions.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>
This commit is contained in:
Peter Ujfalusi 2012-03-08 11:08:36 +02:00 committed by Liam Girdwood
parent 73c9522e76
commit 40c0764b18
1 changed files with 44 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

46
arch/arm/mach-omap2/mcbsp.c
View file

@ -34,7 +34,7 @@
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"
/* McBSP internal signal muxing function */
/* McBSP1 internal signal muxing function for OMAP2/3 */
static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
const char *src)
{
@ -65,6 +65,42 @@ static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
return 0;
}
/* McBSP4 internal signal muxing function for OMAP4 */
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
const char *src)
{
u32 v;
/*
* In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
* mux) is used */
v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
if (!strcmp(signal, "clkr")) {
if (!strcmp(src, "clkr"))
v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
else if (!strcmp(src, "clkx"))
v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
else
return -EINVAL;
} else if (!strcmp(signal, "fsr")) {
if (!strcmp(src, "fsr"))
v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
else if (!strcmp(src, "fsx"))
v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
else
return -EINVAL;
} else {
return -EINVAL;
}
omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
return 0;
}
/* McBSP CLKS source switching function */
static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
const char *src)
@ -146,9 +182,15 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
pdata->has_ccr = true;
}
pdata->set_clk_src = omap2_mcbsp_set_clk_src;
if (id == 1)
/* On OMAP2/3 the McBSP1 port has 6 pin configuration */
if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
/* On OMAP4 the McBSP4 port has 6 pin configuration */
if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
if (id == 2)
/* The FIFO has 1024 + 256 locations */