drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
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@ -627,6 +627,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
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/*
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* For DP rev.1.1, Maximum link rate of Main Link lanes
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* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
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* For DP rev.1.2, Maximum link rate of Main Link lanes
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* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
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*/
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analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
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*bandwidth = data;
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@ -647,7 +649,7 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
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static void analogix_dp_init_training(struct analogix_dp_device *dp,
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enum link_lane_count_type max_lane,
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enum link_rate_type max_rate)
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int max_rate)
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{
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/*
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* MACRO_RST must be applied after the PLL_LOCK to avoid
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@ -659,11 +661,12 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
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analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
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analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
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if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
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(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
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if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
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(dp->link_train.link_rate != DP_LINK_BW_2_7) &&
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(dp->link_train.link_rate != DP_LINK_BW_5_4)) {
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dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
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dp->link_train.link_rate);
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dp->link_train.link_rate = LINK_RATE_1_62GBPS;
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dp->link_train.link_rate = DP_LINK_BW_1_62;
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}
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if (dp->link_train.lane_count == 0) {
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@ -901,9 +904,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
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analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
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analogix_dp_enable_enhanced_mode(dp, 1);
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analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
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analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
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analogix_dp_init_video(dp);
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ret = analogix_dp_config_video(dp);
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if (ret)
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@ -20,11 +20,6 @@
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 5
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enum link_rate_type {
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LINK_RATE_1_62GBPS = 0x06,
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LINK_RATE_2_70GBPS = 0x0a
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};
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enum link_lane_count_type {
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LANE_COUNT1 = 1,
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LANE_COUNT2 = 2,
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@ -128,7 +123,7 @@ struct video_info {
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enum color_coefficient ycbcr_coeff;
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enum color_depth color_depth;
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enum link_rate_type link_rate;
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int link_rate;
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enum link_lane_count_type lane_count;
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};
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@ -855,7 +855,7 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
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u32 reg;
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reg = bwtype;
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if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
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if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
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writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
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}
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