MIPS: Octeon: Update SOC PCI related register definitions for new chips.
Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
David Daney
Ralf Baechle
parent
37d3bfd992
commit
412394d104
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@ -0,0 +1,643 @@
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2011 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_DPI_DEFS_H__
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#define __CVMX_DPI_DEFS_H__
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#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
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#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
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#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
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#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
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#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
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#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
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#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
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#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
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#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
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#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
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#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
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#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
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#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
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#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
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#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
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#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
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#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
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#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
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#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
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union cvmx_dpi_bist_status {
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uint64_t u64;
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struct cvmx_dpi_bist_status_s {
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uint64_t reserved_47_63:17;
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uint64_t bist:47;
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} s;
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struct cvmx_dpi_bist_status_s cn61xx;
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struct cvmx_dpi_bist_status_cn63xx {
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uint64_t reserved_45_63:19;
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uint64_t bist:45;
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} cn63xx;
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struct cvmx_dpi_bist_status_cn63xxp1 {
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uint64_t reserved_37_63:27;
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uint64_t bist:37;
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} cn63xxp1;
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struct cvmx_dpi_bist_status_s cn66xx;
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struct cvmx_dpi_bist_status_cn63xx cn68xx;
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struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
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};
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union cvmx_dpi_ctl {
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uint64_t u64;
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struct cvmx_dpi_ctl_s {
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uint64_t reserved_2_63:62;
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uint64_t clk:1;
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uint64_t en:1;
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} s;
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struct cvmx_dpi_ctl_cn61xx {
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uint64_t reserved_1_63:63;
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uint64_t en:1;
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} cn61xx;
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struct cvmx_dpi_ctl_s cn63xx;
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struct cvmx_dpi_ctl_s cn63xxp1;
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struct cvmx_dpi_ctl_s cn66xx;
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struct cvmx_dpi_ctl_s cn68xx;
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struct cvmx_dpi_ctl_s cn68xxp1;
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};
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union cvmx_dpi_dmax_counts {
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uint64_t u64;
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struct cvmx_dpi_dmax_counts_s {
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uint64_t reserved_39_63:25;
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uint64_t fcnt:7;
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uint64_t dbell:32;
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} s;
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struct cvmx_dpi_dmax_counts_s cn61xx;
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struct cvmx_dpi_dmax_counts_s cn63xx;
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struct cvmx_dpi_dmax_counts_s cn63xxp1;
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struct cvmx_dpi_dmax_counts_s cn66xx;
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struct cvmx_dpi_dmax_counts_s cn68xx;
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struct cvmx_dpi_dmax_counts_s cn68xxp1;
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};
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union cvmx_dpi_dmax_dbell {
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uint64_t u64;
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struct cvmx_dpi_dmax_dbell_s {
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uint64_t reserved_16_63:48;
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uint64_t dbell:16;
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} s;
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struct cvmx_dpi_dmax_dbell_s cn61xx;
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struct cvmx_dpi_dmax_dbell_s cn63xx;
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struct cvmx_dpi_dmax_dbell_s cn63xxp1;
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struct cvmx_dpi_dmax_dbell_s cn66xx;
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struct cvmx_dpi_dmax_dbell_s cn68xx;
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struct cvmx_dpi_dmax_dbell_s cn68xxp1;
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};
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union cvmx_dpi_dmax_err_rsp_status {
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uint64_t u64;
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struct cvmx_dpi_dmax_err_rsp_status_s {
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uint64_t reserved_6_63:58;
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uint64_t status:6;
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} s;
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struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
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struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
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struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
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struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
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};
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union cvmx_dpi_dmax_ibuff_saddr {
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uint64_t u64;
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struct cvmx_dpi_dmax_ibuff_saddr_s {
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uint64_t reserved_62_63:2;
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uint64_t csize:14;
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uint64_t reserved_41_47:7;
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uint64_t idle:1;
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uint64_t saddr:33;
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uint64_t reserved_0_6:7;
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} s;
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struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
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uint64_t reserved_62_63:2;
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uint64_t csize:14;
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uint64_t reserved_41_47:7;
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uint64_t idle:1;
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uint64_t reserved_36_39:4;
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uint64_t saddr:29;
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uint64_t reserved_0_6:7;
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} cn61xx;
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struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
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struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
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struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
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struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
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struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
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};
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union cvmx_dpi_dmax_iflight {
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uint64_t u64;
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struct cvmx_dpi_dmax_iflight_s {
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uint64_t reserved_3_63:61;
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uint64_t cnt:3;
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} s;
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struct cvmx_dpi_dmax_iflight_s cn61xx;
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struct cvmx_dpi_dmax_iflight_s cn66xx;
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struct cvmx_dpi_dmax_iflight_s cn68xx;
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struct cvmx_dpi_dmax_iflight_s cn68xxp1;
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};
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union cvmx_dpi_dmax_naddr {
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uint64_t u64;
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struct cvmx_dpi_dmax_naddr_s {
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uint64_t reserved_40_63:24;
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uint64_t addr:40;
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} s;
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struct cvmx_dpi_dmax_naddr_cn61xx {
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uint64_t reserved_36_63:28;
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uint64_t addr:36;
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} cn61xx;
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struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
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struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
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struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
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struct cvmx_dpi_dmax_naddr_s cn68xx;
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struct cvmx_dpi_dmax_naddr_s cn68xxp1;
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};
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union cvmx_dpi_dmax_reqbnk0 {
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uint64_t u64;
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struct cvmx_dpi_dmax_reqbnk0_s {
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uint64_t state:64;
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} s;
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struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
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struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
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struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
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struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
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struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
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struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
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};
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union cvmx_dpi_dmax_reqbnk1 {
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uint64_t u64;
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struct cvmx_dpi_dmax_reqbnk1_s {
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uint64_t state:64;
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} s;
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struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
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struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
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struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
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struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
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struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
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struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
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};
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union cvmx_dpi_dma_control {
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uint64_t u64;
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struct cvmx_dpi_dma_control_s {
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uint64_t reserved_62_63:2;
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uint64_t dici_mode:1;
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uint64_t pkt_en1:1;
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uint64_t ffp_dis:1;
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uint64_t commit_mode:1;
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uint64_t pkt_hp:1;
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uint64_t pkt_en:1;
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uint64_t reserved_54_55:2;
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uint64_t dma_enb:6;
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uint64_t reserved_34_47:14;
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uint64_t b0_lend:1;
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uint64_t dwb_denb:1;
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uint64_t dwb_ichk:9;
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uint64_t fpa_que:3;
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uint64_t o_add1:1;
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uint64_t o_ro:1;
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uint64_t o_ns:1;
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uint64_t o_es:2;
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uint64_t o_mode:1;
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uint64_t reserved_0_13:14;
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} s;
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struct cvmx_dpi_dma_control_s cn61xx;
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struct cvmx_dpi_dma_control_cn63xx {
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uint64_t reserved_61_63:3;
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uint64_t pkt_en1:1;
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uint64_t ffp_dis:1;
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uint64_t commit_mode:1;
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uint64_t pkt_hp:1;
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uint64_t pkt_en:1;
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uint64_t reserved_54_55:2;
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uint64_t dma_enb:6;
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uint64_t reserved_34_47:14;
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uint64_t b0_lend:1;
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uint64_t dwb_denb:1;
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uint64_t dwb_ichk:9;
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uint64_t fpa_que:3;
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uint64_t o_add1:1;
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uint64_t o_ro:1;
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uint64_t o_ns:1;
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uint64_t o_es:2;
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uint64_t o_mode:1;
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uint64_t reserved_0_13:14;
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} cn63xx;
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struct cvmx_dpi_dma_control_cn63xxp1 {
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uint64_t reserved_59_63:5;
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uint64_t commit_mode:1;
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uint64_t pkt_hp:1;
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uint64_t pkt_en:1;
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uint64_t reserved_54_55:2;
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uint64_t dma_enb:6;
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uint64_t reserved_34_47:14;
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uint64_t b0_lend:1;
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uint64_t dwb_denb:1;
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uint64_t dwb_ichk:9;
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uint64_t fpa_que:3;
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uint64_t o_add1:1;
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uint64_t o_ro:1;
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uint64_t o_ns:1;
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uint64_t o_es:2;
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uint64_t o_mode:1;
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uint64_t reserved_0_13:14;
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} cn63xxp1;
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struct cvmx_dpi_dma_control_cn63xx cn66xx;
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struct cvmx_dpi_dma_control_s cn68xx;
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struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
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};
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union cvmx_dpi_dma_engx_en {
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uint64_t u64;
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struct cvmx_dpi_dma_engx_en_s {
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uint64_t reserved_8_63:56;
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uint64_t qen:8;
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} s;
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struct cvmx_dpi_dma_engx_en_s cn61xx;
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struct cvmx_dpi_dma_engx_en_s cn63xx;
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struct cvmx_dpi_dma_engx_en_s cn63xxp1;
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struct cvmx_dpi_dma_engx_en_s cn66xx;
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struct cvmx_dpi_dma_engx_en_s cn68xx;
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struct cvmx_dpi_dma_engx_en_s cn68xxp1;
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};
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union cvmx_dpi_dma_ppx_cnt {
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uint64_t u64;
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struct cvmx_dpi_dma_ppx_cnt_s {
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uint64_t reserved_16_63:48;
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uint64_t cnt:16;
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} s;
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struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
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struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
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};
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union cvmx_dpi_engx_buf {
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uint64_t u64;
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struct cvmx_dpi_engx_buf_s {
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uint64_t reserved_37_63:27;
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uint64_t compblks:5;
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uint64_t reserved_9_31:23;
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uint64_t base:5;
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uint64_t blks:4;
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} s;
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struct cvmx_dpi_engx_buf_s cn61xx;
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struct cvmx_dpi_engx_buf_cn63xx {
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uint64_t reserved_8_63:56;
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uint64_t base:4;
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uint64_t blks:4;
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} cn63xx;
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struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
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struct cvmx_dpi_engx_buf_s cn66xx;
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struct cvmx_dpi_engx_buf_s cn68xx;
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struct cvmx_dpi_engx_buf_s cn68xxp1;
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};
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union cvmx_dpi_info_reg {
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uint64_t u64;
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struct cvmx_dpi_info_reg_s {
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uint64_t reserved_8_63:56;
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uint64_t ffp:4;
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uint64_t reserved_2_3:2;
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uint64_t ncb:1;
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uint64_t rsl:1;
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} s;
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struct cvmx_dpi_info_reg_s cn61xx;
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struct cvmx_dpi_info_reg_s cn63xx;
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struct cvmx_dpi_info_reg_cn63xxp1 {
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uint64_t reserved_2_63:62;
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||||
uint64_t ncb:1;
|
||||
uint64_t rsl:1;
|
||||
} cn63xxp1;
|
||||
struct cvmx_dpi_info_reg_s cn66xx;
|
||||
struct cvmx_dpi_info_reg_s cn68xx;
|
||||
struct cvmx_dpi_info_reg_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_int_en {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_int_en_s {
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t sprt3_rst:1;
|
||||
uint64_t sprt2_rst:1;
|
||||
uint64_t sprt1_rst:1;
|
||||
uint64_t sprt0_rst:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t req_badfil:1;
|
||||
uint64_t req_inull:1;
|
||||
uint64_t req_anull:1;
|
||||
uint64_t req_undflw:1;
|
||||
uint64_t req_ovrflw:1;
|
||||
uint64_t req_badlen:1;
|
||||
uint64_t req_badadr:1;
|
||||
uint64_t dmadbo:8;
|
||||
uint64_t reserved_2_7:6;
|
||||
uint64_t nfovr:1;
|
||||
uint64_t nderr:1;
|
||||
} s;
|
||||
struct cvmx_dpi_int_en_s cn61xx;
|
||||
struct cvmx_dpi_int_en_cn63xx {
|
||||
uint64_t reserved_26_63:38;
|
||||
uint64_t sprt1_rst:1;
|
||||
uint64_t sprt0_rst:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t req_badfil:1;
|
||||
uint64_t req_inull:1;
|
||||
uint64_t req_anull:1;
|
||||
uint64_t req_undflw:1;
|
||||
uint64_t req_ovrflw:1;
|
||||
uint64_t req_badlen:1;
|
||||
uint64_t req_badadr:1;
|
||||
uint64_t dmadbo:8;
|
||||
uint64_t reserved_2_7:6;
|
||||
uint64_t nfovr:1;
|
||||
uint64_t nderr:1;
|
||||
} cn63xx;
|
||||
struct cvmx_dpi_int_en_cn63xx cn63xxp1;
|
||||
struct cvmx_dpi_int_en_s cn66xx;
|
||||
struct cvmx_dpi_int_en_cn63xx cn68xx;
|
||||
struct cvmx_dpi_int_en_cn63xx cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_int_reg {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_int_reg_s {
|
||||
uint64_t reserved_28_63:36;
|
||||
uint64_t sprt3_rst:1;
|
||||
uint64_t sprt2_rst:1;
|
||||
uint64_t sprt1_rst:1;
|
||||
uint64_t sprt0_rst:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t req_badfil:1;
|
||||
uint64_t req_inull:1;
|
||||
uint64_t req_anull:1;
|
||||
uint64_t req_undflw:1;
|
||||
uint64_t req_ovrflw:1;
|
||||
uint64_t req_badlen:1;
|
||||
uint64_t req_badadr:1;
|
||||
uint64_t dmadbo:8;
|
||||
uint64_t reserved_2_7:6;
|
||||
uint64_t nfovr:1;
|
||||
uint64_t nderr:1;
|
||||
} s;
|
||||
struct cvmx_dpi_int_reg_s cn61xx;
|
||||
struct cvmx_dpi_int_reg_cn63xx {
|
||||
uint64_t reserved_26_63:38;
|
||||
uint64_t sprt1_rst:1;
|
||||
uint64_t sprt0_rst:1;
|
||||
uint64_t reserved_23_23:1;
|
||||
uint64_t req_badfil:1;
|
||||
uint64_t req_inull:1;
|
||||
uint64_t req_anull:1;
|
||||
uint64_t req_undflw:1;
|
||||
uint64_t req_ovrflw:1;
|
||||
uint64_t req_badlen:1;
|
||||
uint64_t req_badadr:1;
|
||||
uint64_t dmadbo:8;
|
||||
uint64_t reserved_2_7:6;
|
||||
uint64_t nfovr:1;
|
||||
uint64_t nderr:1;
|
||||
} cn63xx;
|
||||
struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
|
||||
struct cvmx_dpi_int_reg_s cn66xx;
|
||||
struct cvmx_dpi_int_reg_cn63xx cn68xx;
|
||||
struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_ncbx_cfg {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_ncbx_cfg_s {
|
||||
uint64_t reserved_6_63:58;
|
||||
uint64_t molr:6;
|
||||
} s;
|
||||
struct cvmx_dpi_ncbx_cfg_s cn61xx;
|
||||
struct cvmx_dpi_ncbx_cfg_s cn66xx;
|
||||
struct cvmx_dpi_ncbx_cfg_s cn68xx;
|
||||
};
|
||||
|
||||
union cvmx_dpi_pint_info {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_pint_info_s {
|
||||
uint64_t reserved_14_63:50;
|
||||
uint64_t iinfo:6;
|
||||
uint64_t reserved_6_7:2;
|
||||
uint64_t sinfo:6;
|
||||
} s;
|
||||
struct cvmx_dpi_pint_info_s cn61xx;
|
||||
struct cvmx_dpi_pint_info_s cn63xx;
|
||||
struct cvmx_dpi_pint_info_s cn63xxp1;
|
||||
struct cvmx_dpi_pint_info_s cn66xx;
|
||||
struct cvmx_dpi_pint_info_s cn68xx;
|
||||
struct cvmx_dpi_pint_info_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_pkt_err_rsp {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_pkt_err_rsp_s {
|
||||
uint64_t reserved_1_63:63;
|
||||
uint64_t pkterr:1;
|
||||
} s;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn61xx;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn63xx;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn66xx;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn68xx;
|
||||
struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_err_rsp {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_err_rsp_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t qerr:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_err_rsp_s cn61xx;
|
||||
struct cvmx_dpi_req_err_rsp_s cn63xx;
|
||||
struct cvmx_dpi_req_err_rsp_s cn63xxp1;
|
||||
struct cvmx_dpi_req_err_rsp_s cn66xx;
|
||||
struct cvmx_dpi_req_err_rsp_s cn68xx;
|
||||
struct cvmx_dpi_req_err_rsp_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_err_rsp_en {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_err_rsp_en_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t en:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn61xx;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn63xx;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn66xx;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn68xx;
|
||||
struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_err_rst {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_err_rst_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t qerr:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_err_rst_s cn61xx;
|
||||
struct cvmx_dpi_req_err_rst_s cn63xx;
|
||||
struct cvmx_dpi_req_err_rst_s cn63xxp1;
|
||||
struct cvmx_dpi_req_err_rst_s cn66xx;
|
||||
struct cvmx_dpi_req_err_rst_s cn68xx;
|
||||
struct cvmx_dpi_req_err_rst_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_err_rst_en {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_err_rst_en_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t en:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn61xx;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn63xx;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn66xx;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn68xx;
|
||||
struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_err_skip_comp {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_err_skip_comp_s {
|
||||
uint64_t reserved_24_63:40;
|
||||
uint64_t en_rst:8;
|
||||
uint64_t reserved_8_15:8;
|
||||
uint64_t en_rsp:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_err_skip_comp_s cn61xx;
|
||||
struct cvmx_dpi_req_err_skip_comp_s cn66xx;
|
||||
struct cvmx_dpi_req_err_skip_comp_s cn68xx;
|
||||
struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_req_gbl_en {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_req_gbl_en_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t qen:8;
|
||||
} s;
|
||||
struct cvmx_dpi_req_gbl_en_s cn61xx;
|
||||
struct cvmx_dpi_req_gbl_en_s cn63xx;
|
||||
struct cvmx_dpi_req_gbl_en_s cn63xxp1;
|
||||
struct cvmx_dpi_req_gbl_en_s cn66xx;
|
||||
struct cvmx_dpi_req_gbl_en_s cn68xx;
|
||||
struct cvmx_dpi_req_gbl_en_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_sli_prtx_cfg {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_sli_prtx_cfg_s {
|
||||
uint64_t reserved_25_63:39;
|
||||
uint64_t halt:1;
|
||||
uint64_t qlm_cfg:4;
|
||||
uint64_t reserved_17_19:3;
|
||||
uint64_t rd_mode:1;
|
||||
uint64_t reserved_14_15:2;
|
||||
uint64_t molr:6;
|
||||
uint64_t mps_lim:1;
|
||||
uint64_t reserved_5_6:2;
|
||||
uint64_t mps:1;
|
||||
uint64_t mrrs_lim:1;
|
||||
uint64_t reserved_2_2:1;
|
||||
uint64_t mrrs:2;
|
||||
} s;
|
||||
struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
|
||||
struct cvmx_dpi_sli_prtx_cfg_cn63xx {
|
||||
uint64_t reserved_25_63:39;
|
||||
uint64_t halt:1;
|
||||
uint64_t reserved_21_23:3;
|
||||
uint64_t qlm_cfg:1;
|
||||
uint64_t reserved_17_19:3;
|
||||
uint64_t rd_mode:1;
|
||||
uint64_t reserved_14_15:2;
|
||||
uint64_t molr:6;
|
||||
uint64_t mps_lim:1;
|
||||
uint64_t reserved_5_6:2;
|
||||
uint64_t mps:1;
|
||||
uint64_t mrrs_lim:1;
|
||||
uint64_t reserved_2_2:1;
|
||||
uint64_t mrrs:2;
|
||||
} cn63xx;
|
||||
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
|
||||
struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
|
||||
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
|
||||
struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_sli_prtx_err {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_sli_prtx_err_s {
|
||||
uint64_t addr:61;
|
||||
uint64_t reserved_0_2:3;
|
||||
} s;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn61xx;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn63xx;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn66xx;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn68xx;
|
||||
struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_dpi_sli_prtx_err_info {
|
||||
uint64_t u64;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s {
|
||||
uint64_t reserved_9_63:55;
|
||||
uint64_t lock:1;
|
||||
uint64_t reserved_5_7:3;
|
||||
uint64_t type:1;
|
||||
uint64_t reserved_3_3:1;
|
||||
uint64_t reqq:3;
|
||||
} s;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
|
||||
struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2010 Cavium Networks
|
||||
* Copyright (c) 2003-2011 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
|
||||
#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
|
||||
#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
|
||||
#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
|
||||
#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
|
||||
#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
|
||||
#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
|
||||
#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,509 @@
|
|||
/***********************license start***************
|
||||
* Author: Cavium Networks
|
||||
*
|
||||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2011 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful, but
|
||||
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
|
||||
* NONINFRINGEMENT. See the GNU General Public License for more
|
||||
* details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this file; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
* or visit http://www.gnu.org/licenses/.
|
||||
*
|
||||
* This file may also be available under a different license from Cavium.
|
||||
* Contact Cavium Networks for more information
|
||||
***********************license end**************************************/
|
||||
|
||||
#ifndef __CVMX_PEMX_DEFS_H__
|
||||
#define __CVMX_PEMX_DEFS_H__
|
||||
|
||||
#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
|
||||
#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
|
||||
#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
|
||||
#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
|
||||
|
||||
union cvmx_pemx_bar1_indexx {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_bar1_indexx_s {
|
||||
uint64_t reserved_20_63:44;
|
||||
uint64_t addr_idx:16;
|
||||
uint64_t ca:1;
|
||||
uint64_t end_swp:2;
|
||||
uint64_t addr_v:1;
|
||||
} s;
|
||||
struct cvmx_pemx_bar1_indexx_s cn61xx;
|
||||
struct cvmx_pemx_bar1_indexx_s cn63xx;
|
||||
struct cvmx_pemx_bar1_indexx_s cn63xxp1;
|
||||
struct cvmx_pemx_bar1_indexx_s cn66xx;
|
||||
struct cvmx_pemx_bar1_indexx_s cn68xx;
|
||||
struct cvmx_pemx_bar1_indexx_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_bar2_mask {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_bar2_mask_s {
|
||||
uint64_t reserved_38_63:26;
|
||||
uint64_t mask:35;
|
||||
uint64_t reserved_0_2:3;
|
||||
} s;
|
||||
struct cvmx_pemx_bar2_mask_s cn61xx;
|
||||
struct cvmx_pemx_bar2_mask_s cn66xx;
|
||||
struct cvmx_pemx_bar2_mask_s cn68xx;
|
||||
struct cvmx_pemx_bar2_mask_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_bar_ctl {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_bar_ctl_s {
|
||||
uint64_t reserved_7_63:57;
|
||||
uint64_t bar1_siz:3;
|
||||
uint64_t bar2_enb:1;
|
||||
uint64_t bar2_esx:2;
|
||||
uint64_t bar2_cax:1;
|
||||
} s;
|
||||
struct cvmx_pemx_bar_ctl_s cn61xx;
|
||||
struct cvmx_pemx_bar_ctl_s cn63xx;
|
||||
struct cvmx_pemx_bar_ctl_s cn63xxp1;
|
||||
struct cvmx_pemx_bar_ctl_s cn66xx;
|
||||
struct cvmx_pemx_bar_ctl_s cn68xx;
|
||||
struct cvmx_pemx_bar_ctl_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_bist_status {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_bist_status_s {
|
||||
uint64_t reserved_8_63:56;
|
||||
uint64_t retry:1;
|
||||
uint64_t rqdata0:1;
|
||||
uint64_t rqdata1:1;
|
||||
uint64_t rqdata2:1;
|
||||
uint64_t rqdata3:1;
|
||||
uint64_t rqhdr1:1;
|
||||
uint64_t rqhdr0:1;
|
||||
uint64_t sot:1;
|
||||
} s;
|
||||
struct cvmx_pemx_bist_status_s cn61xx;
|
||||
struct cvmx_pemx_bist_status_s cn63xx;
|
||||
struct cvmx_pemx_bist_status_s cn63xxp1;
|
||||
struct cvmx_pemx_bist_status_s cn66xx;
|
||||
struct cvmx_pemx_bist_status_s cn68xx;
|
||||
struct cvmx_pemx_bist_status_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_bist_status2 {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_bist_status2_s {
|
||||
uint64_t reserved_10_63:54;
|
||||
uint64_t e2p_cpl:1;
|
||||
uint64_t e2p_n:1;
|
||||
uint64_t e2p_p:1;
|
||||
uint64_t peai_p2e:1;
|
||||
uint64_t pef_tpf1:1;
|
||||
uint64_t pef_tpf0:1;
|
||||
uint64_t pef_tnf:1;
|
||||
uint64_t pef_tcf1:1;
|
||||
uint64_t pef_tc0:1;
|
||||
uint64_t ppf:1;
|
||||
} s;
|
||||
struct cvmx_pemx_bist_status2_s cn61xx;
|
||||
struct cvmx_pemx_bist_status2_s cn63xx;
|
||||
struct cvmx_pemx_bist_status2_s cn63xxp1;
|
||||
struct cvmx_pemx_bist_status2_s cn66xx;
|
||||
struct cvmx_pemx_bist_status2_s cn68xx;
|
||||
struct cvmx_pemx_bist_status2_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_cfg_rd {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_cfg_rd_s {
|
||||
uint64_t data:32;
|
||||
uint64_t addr:32;
|
||||
} s;
|
||||
struct cvmx_pemx_cfg_rd_s cn61xx;
|
||||
struct cvmx_pemx_cfg_rd_s cn63xx;
|
||||
struct cvmx_pemx_cfg_rd_s cn63xxp1;
|
||||
struct cvmx_pemx_cfg_rd_s cn66xx;
|
||||
struct cvmx_pemx_cfg_rd_s cn68xx;
|
||||
struct cvmx_pemx_cfg_rd_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_cfg_wr {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_cfg_wr_s {
|
||||
uint64_t data:32;
|
||||
uint64_t addr:32;
|
||||
} s;
|
||||
struct cvmx_pemx_cfg_wr_s cn61xx;
|
||||
struct cvmx_pemx_cfg_wr_s cn63xx;
|
||||
struct cvmx_pemx_cfg_wr_s cn63xxp1;
|
||||
struct cvmx_pemx_cfg_wr_s cn66xx;
|
||||
struct cvmx_pemx_cfg_wr_s cn68xx;
|
||||
struct cvmx_pemx_cfg_wr_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_cpl_lut_valid {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_cpl_lut_valid_s {
|
||||
uint64_t reserved_32_63:32;
|
||||
uint64_t tag:32;
|
||||
} s;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn61xx;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn63xx;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn66xx;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn68xx;
|
||||
struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_ctl_status {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_ctl_status_s {
|
||||
uint64_t reserved_48_63:16;
|
||||
uint64_t auto_sd:1;
|
||||
uint64_t dnum:5;
|
||||
uint64_t pbus:8;
|
||||
uint64_t reserved_32_33:2;
|
||||
uint64_t cfg_rtry:16;
|
||||
uint64_t reserved_12_15:4;
|
||||
uint64_t pm_xtoff:1;
|
||||
uint64_t pm_xpme:1;
|
||||
uint64_t ob_p_cmd:1;
|
||||
uint64_t reserved_7_8:2;
|
||||
uint64_t nf_ecrc:1;
|
||||
uint64_t dly_one:1;
|
||||
uint64_t lnk_enb:1;
|
||||
uint64_t ro_ctlp:1;
|
||||
uint64_t fast_lm:1;
|
||||
uint64_t inv_ecrc:1;
|
||||
uint64_t inv_lcrc:1;
|
||||
} s;
|
||||
struct cvmx_pemx_ctl_status_s cn61xx;
|
||||
struct cvmx_pemx_ctl_status_s cn63xx;
|
||||
struct cvmx_pemx_ctl_status_s cn63xxp1;
|
||||
struct cvmx_pemx_ctl_status_s cn66xx;
|
||||
struct cvmx_pemx_ctl_status_s cn68xx;
|
||||
struct cvmx_pemx_ctl_status_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_dbg_info {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_dbg_info_s {
|
||||
uint64_t reserved_31_63:33;
|
||||
uint64_t ecrc_e:1;
|
||||
uint64_t rawwpp:1;
|
||||
uint64_t racpp:1;
|
||||
uint64_t ramtlp:1;
|
||||
uint64_t rarwdns:1;
|
||||
uint64_t caar:1;
|
||||
uint64_t racca:1;
|
||||
uint64_t racur:1;
|
||||
uint64_t rauc:1;
|
||||
uint64_t rqo:1;
|
||||
uint64_t fcuv:1;
|
||||
uint64_t rpe:1;
|
||||
uint64_t fcpvwt:1;
|
||||
uint64_t dpeoosd:1;
|
||||
uint64_t rtwdle:1;
|
||||
uint64_t rdwdle:1;
|
||||
uint64_t mre:1;
|
||||
uint64_t rte:1;
|
||||
uint64_t acto:1;
|
||||
uint64_t rvdm:1;
|
||||
uint64_t rumep:1;
|
||||
uint64_t rptamrc:1;
|
||||
uint64_t rpmerc:1;
|
||||
uint64_t rfemrc:1;
|
||||
uint64_t rnfemrc:1;
|
||||
uint64_t rcemrc:1;
|
||||
uint64_t rpoison:1;
|
||||
uint64_t recrce:1;
|
||||
uint64_t rtlplle:1;
|
||||
uint64_t rtlpmal:1;
|
||||
uint64_t spoison:1;
|
||||
} s;
|
||||
struct cvmx_pemx_dbg_info_s cn61xx;
|
||||
struct cvmx_pemx_dbg_info_s cn63xx;
|
||||
struct cvmx_pemx_dbg_info_s cn63xxp1;
|
||||
struct cvmx_pemx_dbg_info_s cn66xx;
|
||||
struct cvmx_pemx_dbg_info_s cn68xx;
|
||||
struct cvmx_pemx_dbg_info_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_dbg_info_en {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_dbg_info_en_s {
|
||||
uint64_t reserved_31_63:33;
|
||||
uint64_t ecrc_e:1;
|
||||
uint64_t rawwpp:1;
|
||||
uint64_t racpp:1;
|
||||
uint64_t ramtlp:1;
|
||||
uint64_t rarwdns:1;
|
||||
uint64_t caar:1;
|
||||
uint64_t racca:1;
|
||||
uint64_t racur:1;
|
||||
uint64_t rauc:1;
|
||||
uint64_t rqo:1;
|
||||
uint64_t fcuv:1;
|
||||
uint64_t rpe:1;
|
||||
uint64_t fcpvwt:1;
|
||||
uint64_t dpeoosd:1;
|
||||
uint64_t rtwdle:1;
|
||||
uint64_t rdwdle:1;
|
||||
uint64_t mre:1;
|
||||
uint64_t rte:1;
|
||||
uint64_t acto:1;
|
||||
uint64_t rvdm:1;
|
||||
uint64_t rumep:1;
|
||||
uint64_t rptamrc:1;
|
||||
uint64_t rpmerc:1;
|
||||
uint64_t rfemrc:1;
|
||||
uint64_t rnfemrc:1;
|
||||
uint64_t rcemrc:1;
|
||||
uint64_t rpoison:1;
|
||||
uint64_t recrce:1;
|
||||
uint64_t rtlplle:1;
|
||||
uint64_t rtlpmal:1;
|
||||
uint64_t spoison:1;
|
||||
} s;
|
||||
struct cvmx_pemx_dbg_info_en_s cn61xx;
|
||||
struct cvmx_pemx_dbg_info_en_s cn63xx;
|
||||
struct cvmx_pemx_dbg_info_en_s cn63xxp1;
|
||||
struct cvmx_pemx_dbg_info_en_s cn66xx;
|
||||
struct cvmx_pemx_dbg_info_en_s cn68xx;
|
||||
struct cvmx_pemx_dbg_info_en_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_diag_status {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_diag_status_s {
|
||||
uint64_t reserved_4_63:60;
|
||||
uint64_t pm_dst:1;
|
||||
uint64_t pm_stat:1;
|
||||
uint64_t pm_en:1;
|
||||
uint64_t aux_en:1;
|
||||
} s;
|
||||
struct cvmx_pemx_diag_status_s cn61xx;
|
||||
struct cvmx_pemx_diag_status_s cn63xx;
|
||||
struct cvmx_pemx_diag_status_s cn63xxp1;
|
||||
struct cvmx_pemx_diag_status_s cn66xx;
|
||||
struct cvmx_pemx_diag_status_s cn68xx;
|
||||
struct cvmx_pemx_diag_status_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_inb_read_credits {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_inb_read_credits_s {
|
||||
uint64_t reserved_6_63:58;
|
||||
uint64_t num:6;
|
||||
} s;
|
||||
struct cvmx_pemx_inb_read_credits_s cn61xx;
|
||||
struct cvmx_pemx_inb_read_credits_s cn66xx;
|
||||
struct cvmx_pemx_inb_read_credits_s cn68xx;
|
||||
};
|
||||
|
||||
union cvmx_pemx_int_enb {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_int_enb_s {
|
||||
uint64_t reserved_14_63:50;
|
||||
uint64_t crs_dr:1;
|
||||
uint64_t crs_er:1;
|
||||
uint64_t rdlk:1;
|
||||
uint64_t exc:1;
|
||||
uint64_t un_bx:1;
|
||||
uint64_t un_b2:1;
|
||||
uint64_t un_b1:1;
|
||||
uint64_t up_bx:1;
|
||||
uint64_t up_b2:1;
|
||||
uint64_t up_b1:1;
|
||||
uint64_t pmem:1;
|
||||
uint64_t pmei:1;
|
||||
uint64_t se:1;
|
||||
uint64_t aeri:1;
|
||||
} s;
|
||||
struct cvmx_pemx_int_enb_s cn61xx;
|
||||
struct cvmx_pemx_int_enb_s cn63xx;
|
||||
struct cvmx_pemx_int_enb_s cn63xxp1;
|
||||
struct cvmx_pemx_int_enb_s cn66xx;
|
||||
struct cvmx_pemx_int_enb_s cn68xx;
|
||||
struct cvmx_pemx_int_enb_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_int_enb_int {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_int_enb_int_s {
|
||||
uint64_t reserved_14_63:50;
|
||||
uint64_t crs_dr:1;
|
||||
uint64_t crs_er:1;
|
||||
uint64_t rdlk:1;
|
||||
uint64_t exc:1;
|
||||
uint64_t un_bx:1;
|
||||
uint64_t un_b2:1;
|
||||
uint64_t un_b1:1;
|
||||
uint64_t up_bx:1;
|
||||
uint64_t up_b2:1;
|
||||
uint64_t up_b1:1;
|
||||
uint64_t pmem:1;
|
||||
uint64_t pmei:1;
|
||||
uint64_t se:1;
|
||||
uint64_t aeri:1;
|
||||
} s;
|
||||
struct cvmx_pemx_int_enb_int_s cn61xx;
|
||||
struct cvmx_pemx_int_enb_int_s cn63xx;
|
||||
struct cvmx_pemx_int_enb_int_s cn63xxp1;
|
||||
struct cvmx_pemx_int_enb_int_s cn66xx;
|
||||
struct cvmx_pemx_int_enb_int_s cn68xx;
|
||||
struct cvmx_pemx_int_enb_int_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_int_sum {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_int_sum_s {
|
||||
uint64_t reserved_14_63:50;
|
||||
uint64_t crs_dr:1;
|
||||
uint64_t crs_er:1;
|
||||
uint64_t rdlk:1;
|
||||
uint64_t exc:1;
|
||||
uint64_t un_bx:1;
|
||||
uint64_t un_b2:1;
|
||||
uint64_t un_b1:1;
|
||||
uint64_t up_bx:1;
|
||||
uint64_t up_b2:1;
|
||||
uint64_t up_b1:1;
|
||||
uint64_t pmem:1;
|
||||
uint64_t pmei:1;
|
||||
uint64_t se:1;
|
||||
uint64_t aeri:1;
|
||||
} s;
|
||||
struct cvmx_pemx_int_sum_s cn61xx;
|
||||
struct cvmx_pemx_int_sum_s cn63xx;
|
||||
struct cvmx_pemx_int_sum_s cn63xxp1;
|
||||
struct cvmx_pemx_int_sum_s cn66xx;
|
||||
struct cvmx_pemx_int_sum_s cn68xx;
|
||||
struct cvmx_pemx_int_sum_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_p2n_bar0_start {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_p2n_bar0_start_s {
|
||||
uint64_t addr:50;
|
||||
uint64_t reserved_0_13:14;
|
||||
} s;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn61xx;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn63xx;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn66xx;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn68xx;
|
||||
struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_p2n_bar1_start {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_p2n_bar1_start_s {
|
||||
uint64_t addr:38;
|
||||
uint64_t reserved_0_25:26;
|
||||
} s;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn61xx;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn63xx;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn66xx;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn68xx;
|
||||
struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_p2n_bar2_start {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_p2n_bar2_start_s {
|
||||
uint64_t addr:23;
|
||||
uint64_t reserved_0_40:41;
|
||||
} s;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn61xx;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn63xx;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn66xx;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn68xx;
|
||||
struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_p2p_barx_end {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_p2p_barx_end_s {
|
||||
uint64_t addr:52;
|
||||
uint64_t reserved_0_11:12;
|
||||
} s;
|
||||
struct cvmx_pemx_p2p_barx_end_s cn63xx;
|
||||
struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
|
||||
struct cvmx_pemx_p2p_barx_end_s cn66xx;
|
||||
struct cvmx_pemx_p2p_barx_end_s cn68xx;
|
||||
struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_p2p_barx_start {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_p2p_barx_start_s {
|
||||
uint64_t addr:52;
|
||||
uint64_t reserved_0_11:12;
|
||||
} s;
|
||||
struct cvmx_pemx_p2p_barx_start_s cn63xx;
|
||||
struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
|
||||
struct cvmx_pemx_p2p_barx_start_s cn66xx;
|
||||
struct cvmx_pemx_p2p_barx_start_s cn68xx;
|
||||
struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
|
||||
};
|
||||
|
||||
union cvmx_pemx_tlp_credits {
|
||||
uint64_t u64;
|
||||
struct cvmx_pemx_tlp_credits_s {
|
||||
uint64_t reserved_56_63:8;
|
||||
uint64_t peai_ppf:8;
|
||||
uint64_t pem_cpl:8;
|
||||
uint64_t pem_np:8;
|
||||
uint64_t pem_p:8;
|
||||
uint64_t sli_cpl:8;
|
||||
uint64_t sli_np:8;
|
||||
uint64_t sli_p:8;
|
||||
} s;
|
||||
struct cvmx_pemx_tlp_credits_cn61xx {
|
||||
uint64_t reserved_56_63:8;
|
||||
uint64_t peai_ppf:8;
|
||||
uint64_t reserved_24_47:24;
|
||||
uint64_t sli_cpl:8;
|
||||
uint64_t sli_np:8;
|
||||
uint64_t sli_p:8;
|
||||
} cn61xx;
|
||||
struct cvmx_pemx_tlp_credits_s cn63xx;
|
||||
struct cvmx_pemx_tlp_credits_s cn63xxp1;
|
||||
struct cvmx_pemx_tlp_credits_s cn66xx;
|
||||
struct cvmx_pemx_tlp_credits_s cn68xx;
|
||||
struct cvmx_pemx_tlp_credits_s cn68xxp1;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
* Contact: support@caviumnetworks.com
|
||||
* This file is part of the OCTEON SDK
|
||||
*
|
||||
* Copyright (c) 2003-2010 Cavium Networks
|
||||
* Copyright (c) 2003-2011 Cavium Networks
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, Version 2, as
|
||||
|
|
@ -25,13 +25,6 @@
|
|||
* Contact Cavium Networks for more information
|
||||
***********************license end**************************************/
|
||||
|
||||
/**
|
||||
* cvmx-pexp-defs.h
|
||||
*
|
||||
* Configuration and status register (CSR) definitions for
|
||||
* OCTEON PEXP.
|
||||
*
|
||||
*/
|
||||
#ifndef __CVMX_PEXP_DEFS_H__
|
||||
#define __CVMX_PEXP_DEFS_H__
|
||||
|
||||
|
|
@ -139,7 +132,7 @@
|
|||
#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
|
||||
#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
|
||||
#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
|
||||
#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
|
||||
#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
|
||||
#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
|
||||
#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
|
||||
#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
|
||||
|
|
@ -152,7 +145,10 @@
|
|||
#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
|
||||
#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
|
||||
#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
|
||||
#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
|
||||
#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
|
||||
#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
|
||||
#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
|
||||
#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
|
||||
#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
|
||||
#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
|
||||
|
|
@ -206,6 +202,7 @@
|
|||
#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
|
||||
#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
|
||||
#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
|
||||
#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
|
||||
#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
|
||||
#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
|
||||
#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
|
||||
|
|
@ -214,12 +211,14 @@
|
|||
#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
|
||||
#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
|
||||
#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
|
||||
#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
|
||||
#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
|
||||
#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
|
||||
#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
|
||||
#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
|
||||
#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
|
||||
#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
|
||||
#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
|
||||
#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
|
||||
#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue