drm/radeon/kms: reprogram format in set base.
This should in theory fix the problem with a mode set being required for adjusting the color depth. This also adds in the necessary bits to the format tables for 8-bit, though it doesn't work yet. Signed-off-by: Dave Airlie <airlied@redhat.com>
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65cb15a686
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41456df2d4
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@ -488,6 +488,11 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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}
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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fb_format =
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AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
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AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
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break;
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case 15:
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fb_format =
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AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
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@ -341,6 +341,9 @@ void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
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uint32_t crtc_pitch;
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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format = 2;
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break;
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case 15: /* 555 */
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format = 3;
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break;
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@ -401,11 +404,33 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
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uint32_t crtc_pitch, pitch_pixels;
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uint32_t tiling_flags;
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int format;
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uint32_t gen_cntl_reg, gen_cntl_val;
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DRM_DEBUG("\n");
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radeon_fb = to_radeon_framebuffer(crtc->fb);
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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format = 2;
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break;
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case 15: /* 555 */
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format = 3;
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break;
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case 16: /* 565 */
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format = 4;
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break;
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case 24: /* RGB */
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format = 5;
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break;
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case 32: /* xRGB */
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format = 6;
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break;
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default:
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return false;
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}
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obj = radeon_fb->obj;
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if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
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return -EINVAL;
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@ -458,6 +483,9 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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} else {
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int offset = y * pitch_pixels + x;
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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offset *= 1;
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break;
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case 15:
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case 16:
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offset *= 2;
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@ -476,6 +504,16 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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base &= ~7;
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if (radeon_crtc->crtc_id == 1)
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gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
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else
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gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
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gen_cntl_val = RREG32(gen_cntl_reg);
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gen_cntl_val &= ~(0xf << 8);
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gen_cntl_val |= (format << 8);
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WREG32(gen_cntl_reg, gen_cntl_val);
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crtc_offset = (u32)base;
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WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
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@ -526,6 +564,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
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}
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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format = 2;
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break;
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case 15: /* 555 */
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format = 3;
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break;
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