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irqchip/atmel-aic5: Use explicit variable name for the base chip 

To avoid errors, use an explicit variable name when accessing the 'base'
generic chip.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicholas Ferre <nicolas.ferre@atmel.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <sasha.levin@oracle.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <alexandre.belloni@free-electrons.com>
Cc: <Wenyou.Yang@atmel.com>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/1442843173-2390-2-git-send-email-ludovic.desroches@atmel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
hifive-unleashed-5.1
Ludovic Desroches 2015-09-21 15:46:05 +02:00 committed by Thomas Gleixner
parent f94f87ab1a
commit 414a431ad6
1 changed files with 22 additions and 22 deletions
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44
drivers/irqchip/irq-atmel-aic5.c
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@ -71,15 +71,15 @@ static asmlinkage void __exception_irq_entry
aic5_handle(struct pt_regs *regs)
{
struct irq_domain_chip_generic *dgc = aic5_domain->gc;
struct irq_chip_generic *gc = dgc->gc[0];
struct irq_chip_generic *bgc = dgc->gc[0];
u32 irqnr;
u32 irqstat;
irqnr = irq_reg_readl(gc, AT91_AIC5_IVR);
irqstat = irq_reg_readl(gc, AT91_AIC5_ISR);
irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);
irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);
if (!irqstat)
irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);
else
handle_domain_irq(aic5_domain, irqnr, regs);
}
@ -124,13 +124,13 @@ static int aic5_retrigger(struct irq_data *d)
{
struct irq_domain *domain = d->domain;
struct irq_domain_chip_generic *dgc = domain->gc;
struct irq_chip_generic *gc = dgc->gc[0];
struct irq_chip_generic *bgc = dgc->gc[0];
/* Enable interrupt on AIC5 */
irq_gc_lock(gc);
irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(gc, 1, AT91_AIC5_ISCR);
irq_gc_unlock(gc);
irq_gc_lock(bgc);
irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);
irq_gc_unlock(bgc);
return 0;
}
@ -139,17 +139,17 @@ static int aic5_set_type(struct irq_data *d, unsigned type)
{
struct irq_domain *domain = d->domain;
struct irq_domain_chip_generic *dgc = domain->gc;
struct irq_chip_generic *gc = dgc->gc[0];
struct irq_chip_generic *bgc = dgc->gc[0];
unsigned int smr;
int ret;
irq_gc_lock(gc);
irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
smr = irq_reg_readl(gc, AT91_AIC5_SMR);
irq_gc_lock(bgc);
irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);
smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
ret = aic_common_set_type(d, type, &smr);
if (!ret)
irq_reg_writel(gc, smr, AT91_AIC5_SMR);
irq_gc_unlock(gc);
irq_reg_writel(bgc, smr, AT91_AIC5_SMR);
irq_gc_unlock(bgc);
return ret;
}
@ -263,7 +263,7 @@ static int aic5_irq_domain_xlate(struct irq_domain *d,
unsigned int *out_type)
{
struct irq_domain_chip_generic *dgc = d->gc;
struct irq_chip_generic *gc;
struct irq_chip_generic *bgc;
unsigned smr;
int ret;
@ -275,15 +275,15 @@ static int aic5_irq_domain_xlate(struct irq_domain *d,
if (ret)
return ret;
gc = dgc->gc[0];
bgc = dgc->gc[0];
irq_gc_lock(gc);
irq_reg_writel(gc, *out_hwirq, AT91_AIC5_SSR);
smr = irq_reg_readl(gc, AT91_AIC5_SMR);
irq_gc_lock(bgc);
irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);
smr = irq_reg_readl(bgc, AT91_AIC5_SMR);
ret = aic_common_set_priority(intspec[2], &smr);
if (!ret)
irq_reg_writel(gc, intspec[2] | smr, AT91_AIC5_SMR);
irq_gc_unlock(gc);
irq_reg_writel(bgc, intspec[2] | smr, AT91_AIC5_SMR);
irq_gc_unlock(bgc);
return ret;
}