sh: SH-MobileR SH7722 CPU support.
This adds CPU support for the SH7722. Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
parent
5432143464
commit
41504c3972
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@ -6,6 +6,7 @@ obj-$(CONFIG_CPU_SH2) = sh2/
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obj-$(CONFIG_CPU_SH2A) = sh2a/
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obj-$(CONFIG_CPU_SH2A) = sh2a/
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obj-$(CONFIG_CPU_SH3) = sh3/
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obj-$(CONFIG_CPU_SH3) = sh3/
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obj-$(CONFIG_CPU_SH4) = sh4/
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obj-$(CONFIG_CPU_SH4) = sh4/
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obj-$(CONFIG_CPU_SH4A) += sh4a/
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obj-$(CONFIG_UBC_WAKEUP) += ubc.o
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obj-$(CONFIG_UBC_WAKEUP) += ubc.o
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obj-$(CONFIG_SH_ADC) += adc.o
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obj-$(CONFIG_SH_ADC) += adc.o
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@ -12,17 +12,12 @@ obj-$(CONFIG_SH_STORE_QUEUES) += sq.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7750) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
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obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
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obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
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# Primary on-chip clocks (common)
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# Primary on-chip clocks (common)
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ifndef CONFIG_CPU_SH4A
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clock-$(CONFIG_CPU_SH4) := clock-sh4.o
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clock-$(CONFIG_CPU_SH4) := clock-sh4.o
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clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o
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endif
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clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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# Additional clocks by subtype
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# Additional clocks by subtype
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clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
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clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
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@ -119,11 +119,20 @@ int __init detect_cpu_and_cache_system(void)
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break;
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break;
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case 0x3000:
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case 0x3000:
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case 0x3003:
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case 0x3003:
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case 0x3009:
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cpu_data->type = CPU_SH7343;
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cpu_data->type = CPU_SH7343;
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cpu_data->icache.ways = 4;
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cpu_data->icache.ways = 4;
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cpu_data->dcache.ways = 4;
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cpu_data->dcache.ways = 4;
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cpu_data->flags |= CPU_HAS_LLSC;
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cpu_data->flags |= CPU_HAS_LLSC;
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break;
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break;
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case 0x3008:
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if (prr == 0xa0) {
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cpu_data->type = CPU_SH7722;
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cpu_data->icache.ways = 4;
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cpu_data->dcache.ways = 4;
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cpu_data->flags |= CPU_HAS_LLSC;
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}
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break;
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case 0x8000:
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case 0x8000:
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cpu_data->type = CPU_ST40RA;
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cpu_data->type = CPU_ST40RA;
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cpu_data->flags |= CPU_HAS_FPU;
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cpu_data->flags |= CPU_HAS_FPU;
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@ -0,0 +1,19 @@
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#
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# Makefile for the Linux/SuperH SH-4 backends.
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#
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# CPU subtype setup
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7343.o
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obj-y += $(clock-y)
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@ -0,0 +1,99 @@
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/*
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* arch/sh/kernel/cpu/sh4/clock-sh7343.c
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*
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* SH7343/SH7722 support for the clock framework
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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/*
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* SH7343/SH7722 uses a common set of multipliers and divisors, so this
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* is quite simple..
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*/
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static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
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#define pll_calc() (((ctrl_inl(FRQCR) >> 24) & 0x1f) + 1)
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static void master_clk_init(struct clk *clk)
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{
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clk->parent = clk_get(NULL, "cpu_clk");
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}
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static void master_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) & 0x000f);
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clk->rate *= clk->parent->rate * multipliers[idx] / divisors[idx];
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}
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static struct clk_ops sh7343_master_clk_ops = {
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.init = master_clk_init,
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.recalc = master_clk_recalc,
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};
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static void module_clk_init(struct clk *clk)
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{
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clk->parent = NULL;
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clk->rate = CONFIG_SH_PCLK_FREQ;
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}
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static struct clk_ops sh7343_module_clk_ops = {
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.init = module_clk_init,
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};
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static void bus_clk_init(struct clk *clk)
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{
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clk->parent = clk_get(NULL, "cpu_clk");
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}
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) >> 8) & 0x000f;
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clk->rate = clk->parent->rate * multipliers[idx] / divisors[idx];
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}
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static struct clk_ops sh7343_bus_clk_ops = {
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.init = bus_clk_init,
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_init(struct clk *clk)
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{
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clk->parent = clk_get(NULL, "module_clk");
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clk->flags |= CLK_RATE_PROPAGATES;
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clk_set_rate(clk, clk_get_rate(clk));
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}
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static void cpu_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQCR) >> 20) & 0x000f;
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clk->rate = clk->parent->rate * pll_calc() *
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multipliers[idx] / divisors[idx];
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}
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static struct clk_ops sh7343_cpu_clk_ops = {
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.init = cpu_clk_init,
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7343_clk_ops[] = {
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&sh7343_master_clk_ops,
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&sh7343_module_clk_ops,
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&sh7343_bus_clk_ops,
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&sh7343_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7343_clk_ops))
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*ops = sh7343_clk_ops[idx];
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}
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@ -0,0 +1,76 @@
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/*
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* SH7722 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 80, 81, 83, 82 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7722_devices[] __initdata = {
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&sci_device,
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};
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static int __init sh7722_devices_setup(void)
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{
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return platform_add_devices(sh7722_devices,
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ARRAY_SIZE(sh7722_devices));
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}
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__initcall(sh7722_devices_setup);
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static struct ipr_data sh7722_ipr_map[] = {
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/* IRQ, IPR-idx, shift, prio */
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{ 16, 0, 12, 2 }, /* TMU0 */
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{ 17, 0, 8, 2 }, /* TMU1 */
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};
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static unsigned long ipr_offsets[] = {
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0xa4080000, /* 0: IPRA */
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0xa4080004, /* 1: IPRB */
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0xa4080008, /* 2: IPRC */
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0xa408000c, /* 3: IPRD */
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0xa4080010, /* 4: IPRE */
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0xa4080014, /* 5: IPRF */
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0xa4080018, /* 6: IPRG */
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0xa408001c, /* 7: IPRH */
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0xa4080020, /* 8: IPRI */
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0xa4080024, /* 9: IPRJ */
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0xa4080028, /* 10: IPRK */
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0xa408002c, /* 11: IPRL */
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};
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unsigned int map_ipridx_to_addr(int idx)
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{
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if (unlikely(idx >= ARRAY_SIZE(ipr_offsets)))
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return 0;
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return ipr_offsets[idx];
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}
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void __init init_IRQ_ipr(void)
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{
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make_ipr_irq(sh7722_ipr_map, ARRAY_SIZE(sh7722_ipr_map));
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}
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@ -325,14 +325,18 @@ void __init setup_arch(char **cmdline_p)
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ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
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ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
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if (&__rd_start != &__rd_end) {
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if (&__rd_start != &__rd_end) {
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LOADER_TYPE = 1;
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LOADER_TYPE = 1;
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INITRD_START = PHYSADDR((unsigned long)&__rd_start) - __MEMORY_START;
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INITRD_START = PHYSADDR((unsigned long)&__rd_start) -
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INITRD_SIZE = (unsigned long)&__rd_end - (unsigned long)&__rd_start;
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__MEMORY_START;
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INITRD_SIZE = (unsigned long)&__rd_end -
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(unsigned long)&__rd_start;
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}
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}
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if (LOADER_TYPE && INITRD_START) {
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if (LOADER_TYPE && INITRD_START) {
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if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
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if (INITRD_START + INITRD_SIZE <= (max_low_pfn << PAGE_SHIFT)) {
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reserve_bootmem_node(NODE_DATA(0), INITRD_START+__MEMORY_START, INITRD_SIZE);
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reserve_bootmem_node(NODE_DATA(0), INITRD_START +
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initrd_start = INITRD_START + PAGE_OFFSET + __MEMORY_START;
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__MEMORY_START, INITRD_SIZE);
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initrd_start = INITRD_START + PAGE_OFFSET +
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__MEMORY_START;
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initrd_end = initrd_start + INITRD_SIZE;
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initrd_end = initrd_start + INITRD_SIZE;
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} else {
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} else {
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printk("initrd extends beyond end of memory "
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printk("initrd extends beyond end of memory "
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@ -404,7 +408,7 @@ static const char *cpu_name[] = {
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[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
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[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
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[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
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[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
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[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
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[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
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[CPU_SH7785] = "SH7785",
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[CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722",
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[CPU_SH_NONE] = "Unknown"
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[CPU_SH_NONE] = "Unknown"
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};
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};
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@ -35,6 +35,9 @@ config CPU_SUBTYPE_ST40
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select CPU_SH4
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select CPU_SH4
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_INTC2_IRQ
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config CPU_SHX2
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bool
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#
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#
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# Processor subtypes
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# Processor subtypes
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#
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#
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@ -180,6 +183,7 @@ config CPU_SUBTYPE_SH7780
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config CPU_SUBTYPE_SH7785
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config CPU_SUBTYPE_SH7785
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bool "Support SH7785 processor"
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bool "Support SH7785 processor"
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select CPU_SH4A
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select CPU_SH4A
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select CPU_SHX2
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select CPU_HAS_INTC2_IRQ
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select CPU_HAS_INTC2_IRQ
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comment "SH4AL-DSP Processor Support"
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comment "SH4AL-DSP Processor Support"
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@ -192,6 +196,12 @@ config CPU_SUBTYPE_SH7343
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bool "Support SH7343 processor"
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bool "Support SH7343 processor"
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select CPU_SH4AL_DSP
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select CPU_SH4AL_DSP
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config CPU_SUBTYPE_SH7722
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bool "Support SH7722 processor"
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select CPU_SH4AL_DSP
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select CPU_SHX2
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select CPU_HAS_IPR_IRQ
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endmenu
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endmenu
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menu "Memory management options"
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menu "Memory management options"
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@ -250,7 +260,7 @@ config 32BIT
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config X2TLB
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config X2TLB
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bool "Enable extended TLB mode"
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bool "Enable extended TLB mode"
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depends on CPU_SUBTYPE_SH7785 && MMU && EXPERIMENTAL
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depends on CPU_SHX2 && MMU && EXPERIMENTAL
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help
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help
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Selecting this option will enable the extended mode of the SH-X2
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Selecting this option will enable the extended mode of the SH-X2
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TLB. For legacy SH-X behaviour and interoperability, say N. For
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TLB. For legacy SH-X behaviour and interoperability, say N. For
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@ -319,6 +319,28 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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sci_out(port, SCFCR, fcr_val);
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sci_out(port, SCFCR, fcr_val);
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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{
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||||||
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unsigned int fcr_val = 0;
|
||||||
|
|
||||||
|
if (cflag & CRTSCTS) {
|
||||||
|
fcr_val |= SCFCR_MCE;
|
||||||
|
|
||||||
|
ctrl_outw(0x0000, PORT_PSCR);
|
||||||
|
} else {
|
||||||
|
unsigned short data;
|
||||||
|
|
||||||
|
data = ctrl_inw(PORT_PSCR);
|
||||||
|
data &= 0x033f;
|
||||||
|
data |= 0x0400;
|
||||||
|
ctrl_outw(data, PORT_PSCR);
|
||||||
|
|
||||||
|
ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0);
|
||||||
|
}
|
||||||
|
|
||||||
|
sci_out(port, SCFCR, fcr_val);
|
||||||
|
}
|
||||||
#else
|
#else
|
||||||
/* For SH7750 */
|
/* For SH7750 */
|
||||||
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
||||||
|
|
|
@ -90,6 +90,13 @@
|
||||||
# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
|
# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
|
||||||
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
|
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
|
||||||
# define SCIF_ONLY
|
# define SCIF_ONLY
|
||||||
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||||
|
# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
|
||||||
|
# define SCSPTR0 SCPDR0
|
||||||
|
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||||
|
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
|
# define SCIF_ONLY
|
||||||
|
# define PORT_PSCR 0xA405011E
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||||
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
|
||||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||||
|
@ -522,6 +529,13 @@ static inline int sci_rxd_in(struct uart_port *port)
|
||||||
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||||
|
static inline int sci_rxd_in(struct uart_port *port)
|
||||||
|
{
|
||||||
|
if (port->mapbase == 0xffe00000)
|
||||||
|
return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||||
static inline int sci_rxd_in(struct uart_port *port)
|
static inline int sci_rxd_in(struct uart_port *port)
|
||||||
{
|
{
|
||||||
|
|
|
@ -16,9 +16,8 @@
|
||||||
|
|
||||||
static void __init check_bugs(void)
|
static void __init check_bugs(void)
|
||||||
{
|
{
|
||||||
extern char *get_cpu_subtype(void);
|
|
||||||
extern unsigned long loops_per_jiffy;
|
extern unsigned long loops_per_jiffy;
|
||||||
char *p= &init_utsname()->machine[2]; /* "sh" */
|
char *p = &init_utsname()->machine[2]; /* "sh" */
|
||||||
|
|
||||||
cpu_data->loops_per_jiffy = loops_per_jiffy;
|
cpu_data->loops_per_jiffy = loops_per_jiffy;
|
||||||
|
|
||||||
|
@ -40,6 +39,15 @@ static void __init check_bugs(void)
|
||||||
*p++ = '4';
|
*p++ = '4';
|
||||||
*p++ = 'a';
|
*p++ = 'a';
|
||||||
break;
|
break;
|
||||||
|
case CPU_SH73180 ... CPU_SH7722:
|
||||||
|
*p++ = '4';
|
||||||
|
*p++ = 'a';
|
||||||
|
*p++ = 'l';
|
||||||
|
*p++ = '-';
|
||||||
|
*p++ = 'd';
|
||||||
|
*p++ = 's';
|
||||||
|
*p++ = 'p';
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
*p++ = '?';
|
*p++ = '?';
|
||||||
*p++ = '!';
|
*p++ = '!';
|
||||||
|
|
|
@ -22,7 +22,7 @@
|
||||||
#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
|
#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
|
||||||
#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
|
#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
|
||||||
#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
|
#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
|
||||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
#ifndef CONFIG_CPU_SH4A
|
||||||
#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
|
#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -10,7 +10,7 @@
|
||||||
#ifndef __ASM_CPU_SH4_FREQ_H
|
#ifndef __ASM_CPU_SH4_FREQ_H
|
||||||
#define __ASM_CPU_SH4_FREQ_H
|
#define __ASM_CPU_SH4_FREQ_H
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_SUBTYPE_SH73180)
|
#if defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||||
#define FRQCR 0xa4150000
|
#define FRQCR 0xa4150000
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||||
#define FRQCR 0xffc80000
|
#define FRQCR 0xffc80000
|
||||||
|
|
|
@ -37,7 +37,8 @@
|
||||||
# define ONCHIP_NR_IRQS 144
|
# define ONCHIP_NR_IRQS 144
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH73180) || \
|
defined(CONFIG_CPU_SUBTYPE_SH73180) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7343)
|
defined(CONFIG_CPU_SUBTYPE_SH7343) || \
|
||||||
|
defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||||
# define ONCHIP_NR_IRQS 109
|
# define ONCHIP_NR_IRQS 109
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||||
# define ONCHIP_NR_IRQS 111
|
# define ONCHIP_NR_IRQS 111
|
||||||
|
@ -79,6 +80,8 @@
|
||||||
# define OFFCHIP_NR_IRQS 16
|
# define OFFCHIP_NR_IRQS 16
|
||||||
#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
|
#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
|
||||||
# define OFFCHIP_NR_IRQS 12
|
# define OFFCHIP_NR_IRQS 12
|
||||||
|
#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
|
||||||
|
# define OFFCHIP_NR_IRQS 14
|
||||||
#elif defined(CONFIG_SH_UNKNOWN)
|
#elif defined(CONFIG_SH_UNKNOWN)
|
||||||
# define OFFCHIP_NR_IRQS 16 /* Must also be last */
|
# define OFFCHIP_NR_IRQS 16 /* Must also be last */
|
||||||
#else
|
#else
|
||||||
|
|
|
@ -27,6 +27,8 @@
|
||||||
#define CCN_CVR 0xff000040
|
#define CCN_CVR 0xff000040
|
||||||
#define CCN_PRR 0xff000044
|
#define CCN_PRR 0xff000044
|
||||||
|
|
||||||
|
const char *get_cpu_subtype(void);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* CPU type and hardware bug flags. Kept separately for each CPU.
|
* CPU type and hardware bug flags. Kept separately for each CPU.
|
||||||
*
|
*
|
||||||
|
@ -52,8 +54,10 @@ enum cpu_type {
|
||||||
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
|
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
|
||||||
|
|
||||||
/* SH-4A types */
|
/* SH-4A types */
|
||||||
CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
|
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
|
||||||
CPU_SH7785,
|
|
||||||
|
/* SH4AL-DSP types */
|
||||||
|
CPU_SH73180, CPU_SH7343, CPU_SH7722,
|
||||||
|
|
||||||
/* Unknown subtype */
|
/* Unknown subtype */
|
||||||
CPU_SH_NONE
|
CPU_SH_NONE
|
||||||
|
|
Loading…
Reference in New Issue