ARM: cns3xxx: initial DT support
This adds very minimal support for booting cns3xxx using a device tree. It should support the same devices that cns3420vb provides but gets them from the DT. All devices that don't have their own binding are probed through auxdata. This is completely untested and likely incomplete. Booting through ATAGS is made optional, so it can be turned off by anybody who has a DTB file. Signed-off-by: Arnd Bergmann <arnd@arndb.de>hifive-unleashed-5.1
Arnd Bergmann
parent
15bc1fe67f
commit
415f59142d
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@ -14,6 +14,7 @@ menu "CNS3XXX platform type"
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config MACH_CNS3420VB
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bool "Support for CNS3420 Validation Board"
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depends on ATAGS
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help
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Include support for the Cavium Networks CNS3420 MPCore Platform
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Baseboard.
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@ -1,3 +1,5 @@
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obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
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cns3xxx-y += core.o pm.o
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cns3xxx-$(CONFIG_ATAGS) += devices.o
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cns3xxx-$(CONFIG_PCI) += pcie.o
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cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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@ -13,12 +13,18 @@
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "cns3xxx.h"
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#include "core.h"
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#include "pm.h"
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static struct map_desc cns3xxx_io_desc[] __initdata = {
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{
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@ -276,3 +282,116 @@ void __init cns3xxx_l2x0_init(void)
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}
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#endif /* CONFIG_CACHE_L2X0 */
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static int csn3xxx_usb_power_on(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*
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* Set USB AHB INCR length to 16
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*/
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if (atomic_inc_return(&usb_pwr_ref) == 1) {
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cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
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cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
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__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
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MISC_CHIP_CONFIG_REG);
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}
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return 0;
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}
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static void csn3xxx_usb_power_off(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*/
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if (atomic_dec_return(&usb_pwr_ref) == 0)
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cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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}
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static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
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.num_ports = 1,
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
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{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
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{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
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{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
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{ "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
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{},
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};
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static void __init cns3xxx_init(void)
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{
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struct device_node *dn;
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cns3xxx_l2x0_init();
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dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
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if (of_device_is_available(dn)) {
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u32 tmp;
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tmp = __raw_readl(MISC_SATA_POWER_MODE);
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tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
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tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
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__raw_writel(tmp, MISC_SATA_POWER_MODE);
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/* Enable SATA PHY */
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
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cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
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/* Enable SATA Clock */
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cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
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/* De-Asscer SATA Reset */
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
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}
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dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
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if (of_device_is_available(dn)) {
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u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
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u32 gpioa_pins = __raw_readl(gpioa);
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/* MMC/SD pins share with GPIOA */
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gpioa_pins |= 0x1fff0004;
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__raw_writel(gpioa_pins, gpioa);
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cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
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cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
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}
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pm_power_off = cns3xxx_power_off;
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of_platform_populate(NULL, of_default_bus_match_table,
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cns3xxx_auxdata, NULL);
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}
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static const char *cns3xxx_dt_compat[] __initdata = {
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"cavium,cns3410",
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"cavium,cns3420",
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NULL,
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};
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DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
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.dt_compat = cns3xxx_dt_compat,
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.nr_irqs = NR_IRQS_CNS3XXX,
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.map_io = cns3xxx_map_io,
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.init_irq = cns3xxx_init_irq,
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.init_time = cns3xxx_timer_init,
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.init_machine = cns3xxx_init,
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.restart = cns3xxx_restart,
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MACHINE_END
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