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Merge branch 'fix' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into fixes

hifive-unleashed-5.1
Arnd Bergmann 2011-08-12 15:49:38 +00:00
parent 143ed290f0 af9dafb1dc
commit 419bb4e064
5 changed files with 94 additions and 85 deletions
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6
arch/arm/kernel/iwmmxt.S
View File

@ -195,10 +195,10 @@ ENTRY(iwmmxt_task_disable)
@ enable access to CP0 and CP1
XSC(mrc p15, 0, r4, c15, c1, 0)
XSC(orr r4, r4, #0xf)
XSC(orr r4, r4, #0x3)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(mrc p15, 0, r4, c1, c0, 2)
PJ4(orr r4, r4, #0x3)
PJ4(orr r4, r4, #0xf)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mov r0, #0 @ nothing to load
@ -313,7 +313,7 @@ ENTRY(iwmmxt_task_switch)
teq r2, r3 @ next task owns it?
movne pc, lr @ no: leave Concan disabled
1: @ flip Conan access
1: @ flip Concan access
XSC(eor r1, r1, #0x3)
XSC(mcr p15, 0, r1, c15, c1, 0)
PJ4(eor r1, r1, #0xf)

22
arch/arm/mach-mmp/gplugd.c
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@ -16,16 +16,18 @@
#include <mach/gpio.h>
#include <mach/pxa168.h>
#include <mach/mfp-pxa168.h>
#include <mach/mfp-gplugd.h>
#include "common.h"
static unsigned long gplugd_pin_config[] __initdata = {
/* UART3 */
GPIO8_UART3_SOUT,
GPIO9_UART3_SIN,
GPI1O_UART3_CTS,
GPI11_UART3_RTS,
GPIO8_UART3_TXD,
GPIO9_UART3_RXD,
GPIO1O_UART3_CTS,
GPIO11_UART3_RTS,
/* USB OTG PEN */
GPIO18_GPIO,
/* MMC2 */
GPIO28_MMC2_CMD,
@ -109,6 +111,12 @@ static unsigned long gplugd_pin_config[] __initdata = {
GPIO105_CI2C_SDA,
GPIO106_CI2C_SCL,
/* SPI NOR Flash on SSP2 */
GPIO107_SSP2_RXD,
GPIO108_SSP2_TXD,
GPIO110_GPIO, /* SPI_CSn */
GPIO111_SSP2_CLK,
/* Select JTAG */
GPIO109_GPIO,
@ -154,7 +162,7 @@ static void __init select_disp_freq(void)
"frequency\n");
} else {
gpio_direction_output(35, 1);
gpio_free(104);
gpio_free(35);
}
if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
@ -162,7 +170,7 @@ static void __init select_disp_freq(void)
"frequency\n");
} else {
gpio_direction_output(85, 0);
gpio_free(104);
gpio_free(85);
}
}

52
arch/arm/mach-mmp/include/mach/mfp-gplugd.h
View File

@ -1,52 +0,0 @@
/*
* linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
*
* MFP definitions used in gplugD
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MACH_MFP_GPLUGD_H
#define __MACH_MFP_GPLUGD_H
#include <plat/mfp.h>
#include <mach/mfp.h>
/* UART3 */
#define GPIO8_UART3_SOUT MFP_CFG(GPIO8, AF2)
#define GPIO9_UART3_SIN MFP_CFG(GPIO9, AF2)
#define GPI1O_UART3_CTS MFP_CFG(GPIO10, AF2)
#define GPI11_UART3_RTS MFP_CFG(GPIO11, AF2)
/* MMC2 */
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
/* I2S */
#undef GPIO114_I2S_FRM
#undef GPIO115_I2S_BCLK
#define GPIO114_I2S_FRM MFP_CFG_DRV(GPIO114, AF1, FAST)
#define GPIO115_I2S_BCLK MFP_CFG_DRV(GPIO115, AF1, FAST)
#define GPIO116_I2S_TXD MFP_CFG_DRV(GPIO116, AF1, FAST)
/* MMC4 */
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
/* OTG GPIO */
#define GPIO_USB_OTG_PEN 18
#define GPIO_USB_OIDIR 20
/* Other GPIOs are 35, 84, 85 */
#endif /* __MACH_MFP_GPLUGD_H */

37
arch/arm/mach-mmp/include/mach/mfp-pxa168.h
View File

@ -203,6 +203,10 @@
#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
/* UART */
#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2)
#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2)
#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2)
#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2)
#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2)
#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2)
#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
@ -232,6 +236,22 @@
#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
/* MMC2 */
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
/* MMC4 */
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
/* LCD */
#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
@ -269,11 +289,12 @@
#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1)
/* I2S */
#define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6)
#define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1)
#define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1)
#define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2)
#define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2)
#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6)
#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1)
#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1)
#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2)
#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1)
#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2)
/* PWM */
#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1)
@ -324,4 +345,10 @@
#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
/* SSP2 */
#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4)
#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4)
#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4)
#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4)
#endif /* __ASM_MACH_MFP_PXA168_H */

62
arch/arm/mach-mmp/time.c
View File

@ -51,12 +51,12 @@ static inline uint32_t timer_read(void)
{
int delay = 100;
__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0));
__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
while (delay--)
cpu_relax();
return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
}
unsigned long long notrace sched_clock(void)
@ -75,28 +75,51 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *c = dev_id;
/* disable and clear pending interrupt status */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0));
/*
* Clear pending interrupt status.
*/
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
/*
* Disable timer 0.
*/
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
c->event_handler(c);
return IRQ_HANDLED;
}
static int timer_set_next_event(unsigned long delta,
struct clock_event_device *dev)
{
unsigned long flags, next;
unsigned long flags;
local_irq_save(flags);
/* clear pending interrupt status and enable */
/*
* Disable timer 0.
*/
__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
/*
* Clear and enable timer match 0 interrupt.
*/
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
next = timer_read() + delta;
__raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
/*
* Setup new clockevent timer value.
*/
__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
/*
* Enable timer 0.
*/
__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
local_irq_restore(flags);
return 0;
}
@ -145,23 +168,26 @@ static struct clocksource cksrc = {
static void __init timer_config(void)
{
uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER);
uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR);
__raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3);
ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
/* free-running mode */
__raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR);
/* set timer 0 to periodic mode, and timer 1 to free-running mode */
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */
__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
/* enable timer counter */
__raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER);
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */
__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
/* enable timer 1 counter */
__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
}
static struct irqaction timer_irq = {