ide: remove broken hpt34x driver
No big loss since HPT343/363 controllers are properly supported by pata_hpt3x3 driver from Alan Cox. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>hifive-unleashed-5.1
Bartlomiej Zolnierkiewicz
parent
0df962777b
commit
41d1a3d31d
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@ -328,7 +328,7 @@ config IDEPCI_PCIBUS_ORDER
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# TODO: split it on per host driver config options (or module parameters)
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config BLK_DEV_OFFBOARD
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bool "Boot off-board chipsets first support (DEPRECATED)"
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depends on BLK_DEV_IDEPCI && (BLK_DEV_AEC62XX || BLK_DEV_GENERIC || BLK_DEV_HPT34X || BLK_DEV_HPT366 || BLK_DEV_PDC202XX_NEW || BLK_DEV_PDC202XX_OLD || BLK_DEV_TC86C001)
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depends on BLK_DEV_IDEPCI && (BLK_DEV_AEC62XX || BLK_DEV_GENERIC || BLK_DEV_HPT366 || BLK_DEV_PDC202XX_NEW || BLK_DEV_PDC202XX_OLD || BLK_DEV_TC86C001)
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help
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Normally, IDE controllers built into the motherboard (on-board
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controllers) are assigned to ide0 and ide1 while those on add-in PCI
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@ -478,28 +478,6 @@ config BLK_DEV_CS5535
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It is safe to say Y to this question.
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config BLK_DEV_HPT34X
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tristate "HPT34X chipset support"
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depends on BROKEN
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select BLK_DEV_IDEDMA_PCI
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help
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This driver adds up to 4 more EIDE devices sharing a single
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interrupt. The HPT343 chipset in its current form is a non-bootable
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controller; the HPT345/HPT363 chipset is a bootable (needs BIOS FIX)
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PCI UDMA controllers. This driver requires dynamic tuning of the
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chipset during the ide-probe at boot time. It is reported to support
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DVD II drives, by the manufacturer.
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config HPT34X_AUTODMA
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bool "HPT34X AUTODMA support (EXPERIMENTAL)"
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depends on BLK_DEV_HPT34X && EXPERIMENTAL
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help
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This is a dangerous thing to attempt currently! Please read the
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comments at the top of <file:drivers/ide/pci/hpt34x.c>. If you say Y
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here, then say Y to "Use DMA by default when available" as well.
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If unsure, say N.
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config BLK_DEV_HPT366
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tristate "HPT36X/37X chipset support"
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select BLK_DEV_IDEDMA_PCI
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@ -11,7 +11,6 @@ obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o
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obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
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obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
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obj-$(CONFIG_BLK_DEV_DELKIN) += delkin_cb.o
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obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o
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obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
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obj-$(CONFIG_BLK_DEV_IT8213) += it8213.o
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obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
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@ -1,193 +0,0 @@
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/*
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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*
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* 00:12.0 Unknown mass storage controller:
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* Triones Technologies, Inc.
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* Unknown device 0003 (rev 01)
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*
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* hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
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* hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
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* hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
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* hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
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* hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
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* hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
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*
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* ide-pci.c reference
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*
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* Since there are two cards that report almost identically,
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* the only discernable difference is the values reported in pcicmd.
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* Booting-BIOS card or HPT363 :: pcicmd == 0x07
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* Non-bootable card or HPT343 :: pcicmd == 0x05
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#define DRV_NAME "hpt34x"
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#define HPT343_DEBUG_DRIVE_INFO 0
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static void hpt34x_set_mode(ide_drive_t *drive, const u8 speed)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
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u8 hi_speed, lo_speed;
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hi_speed = speed >> 4;
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lo_speed = speed & 0x0f;
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if (hi_speed & 7) {
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hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
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} else {
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lo_speed <<= 5;
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lo_speed >>= 5;
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}
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pci_read_config_dword(dev, 0x44, ®1);
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pci_read_config_dword(dev, 0x48, ®2);
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tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
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tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
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pci_write_config_dword(dev, 0x44, tmp1);
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pci_write_config_dword(dev, 0x48, tmp2);
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#if HPT343_DEBUG_DRIVE_INFO
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printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
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" (0x%02x 0x%02x)\n",
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drive->name, ide_xfer_verbose(speed),
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drive->dn, reg1, tmp1, reg2, tmp2,
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hi_speed, lo_speed);
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#endif /* HPT343_DEBUG_DRIVE_INFO */
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}
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static void hpt34x_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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hpt34x_set_mode(drive, XFER_PIO_0 + pio);
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}
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/*
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* If the BIOS does not set the IO base addaress to XX00, 343 will fail.
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*/
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#define HPT34X_PCI_INIT_REG 0x80
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static unsigned int init_chipset_hpt34x(struct pci_dev *dev)
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{
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int i = 0;
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unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
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unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
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unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
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u16 cmd;
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unsigned long flags;
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local_irq_save(flags);
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pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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if (cmd & PCI_COMMAND_MEMORY)
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
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else
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
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/*
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* Since 20-23 can be assigned and are R/W, we correct them.
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*/
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pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
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for(i=0; i<4; i++) {
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dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
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dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
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dev->resource[i].flags = IORESOURCE_IO;
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pci_write_config_dword(dev,
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(PCI_BASE_ADDRESS_0 + (i * 4)),
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dev->resource[i].start);
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}
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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local_irq_restore(flags);
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return dev->irq;
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}
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static const struct ide_port_ops hpt34x_port_ops = {
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.set_pio_mode = hpt34x_set_pio_mode,
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.set_dma_mode = hpt34x_set_mode,
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};
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#define IDE_HFLAGS_HPT34X \
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(IDE_HFLAG_NO_ATAPI_DMA | \
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IDE_HFLAG_NO_DSC | \
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IDE_HFLAG_NO_AUTODMA)
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static const struct ide_port_info hpt34x_chipsets[] __devinitdata = {
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{ /* 0: HPT343 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_hpt34x,
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.port_ops = &hpt34x_port_ops,
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.host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_NON_BOOTABLE,
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.pio_mask = ATA_PIO5,
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},
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{ /* 1: HPT345 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_hpt34x,
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.port_ops = &hpt34x_port_ops,
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.host_flags = IDE_HFLAGS_HPT34X | IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO5,
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#ifdef CONFIG_HPT34X_AUTODMA
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.swdma_mask = ATA_SWDMA2,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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#endif
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}
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};
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static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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const struct ide_port_info *d;
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u16 pcicmd = 0;
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pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
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d = &hpt34x_chipsets[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
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return ide_pci_init_one(dev, d, NULL);
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}
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static const struct pci_device_id hpt34x_pci_tbl[] = {
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{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), 0 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
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static struct pci_driver hpt34x_pci_driver = {
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.name = "HPT34x_IDE",
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.id_table = hpt34x_pci_tbl,
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.probe = hpt34x_init_one,
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.remove = ide_pci_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init hpt34x_ide_init(void)
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{
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return ide_pci_register_driver(&hpt34x_pci_driver);
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}
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static void __exit hpt34x_ide_exit(void)
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{
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pci_unregister_driver(&hpt34x_pci_driver);
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}
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module_init(hpt34x_ide_init);
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module_exit(hpt34x_ide_exit);
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MODULE_AUTHOR("Andre Hedrick");
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MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
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MODULE_LICENSE("GPL");
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