drm/amdgpu/ci: sync up with dpm changes from radeon
Looks like radeon commit:
d3052b8ce8
was missed.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
12424e5528
commit
4223cc3de2
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@ -3016,7 +3016,6 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev,
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&memory_level->MinVddcPhases);
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memory_level->EnabledForThrottle = 1;
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memory_level->EnabledForActivity = 1;
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memory_level->UpH = 0;
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memory_level->DownH = 100;
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memory_level->VoltageDownH = 0;
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@ -3375,7 +3374,6 @@ static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
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graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
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graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
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graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
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graphic_level->EnabledForActivity = 1;
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return 0;
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}
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@ -3406,6 +3404,7 @@ static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
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pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
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PPSMC_DISPLAY_WATERMARK_HIGH;
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}
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pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
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pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
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pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
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@ -3449,6 +3448,8 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
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return ret;
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}
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pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
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if ((dpm_table->mclk_table.count >= 2) &&
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((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
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pi->smc_state_table.MemoryLevel[1].MinVddc =
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