PCI: mvebu: Convert to use pci_host_bridge directly
Rather than using the ARM-specific pci_common_init_dev() API, use the pci_host_bridge logic directly. Unfortunately, we can't use devm_of_pci_get_host_bridge_resources(), because the DT binding for describing PCIe apertures for this PCI controller is a bit special, and we cannot retrieve them from the 'ranges' property. Therefore, we still have some special code to handle this. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>hifive-unleashed-5.1
Thomas Petazzoni
Lorenzo Pieralisi
parent
5a553d6ba1
commit
42342073e3
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@ -125,6 +125,7 @@ struct mvebu_pcie {
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struct platform_device *pdev;
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struct mvebu_pcie_port *ports;
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struct msi_controller *msi;
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struct list_head resources;
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struct resource io;
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struct resource realio;
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struct resource mem;
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@ -800,7 +801,7 @@ static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
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static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
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struct mvebu_pcie *pcie = bus->sysdata;
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struct mvebu_pcie_port *port;
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int ret;
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@ -826,7 +827,7 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
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struct mvebu_pcie *pcie = bus->sysdata;
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struct mvebu_pcie_port *port;
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int ret;
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@ -857,36 +858,6 @@ static struct pci_ops mvebu_pcie_ops = {
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.write = mvebu_pcie_wr_conf,
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};
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static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
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{
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struct mvebu_pcie *pcie = sys_to_pcie(sys);
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int err, i;
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pcie->mem.name = "PCI MEM";
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pcie->realio.name = "PCI I/O";
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if (resource_size(&pcie->realio) != 0)
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pci_add_resource_offset(&sys->resources, &pcie->realio,
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sys->io_offset);
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pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
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pci_add_resource(&sys->resources, &pcie->busn);
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err = devm_request_pci_bus_resources(&pcie->pdev->dev, &sys->resources);
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if (err)
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return 0;
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for (i = 0; i < pcie->nports; i++) {
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struct mvebu_pcie_port *port = &pcie->ports[i];
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if (!port->base)
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continue;
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mvebu_pcie_setup_hw(port);
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}
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return 1;
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}
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static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
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const struct resource *res,
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resource_size_t start,
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@ -917,26 +888,6 @@ static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
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return start;
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}
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static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
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{
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struct hw_pci hw;
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memset(&hw, 0, sizeof(hw));
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#ifdef CONFIG_PCI_MSI
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hw.msi_ctrl = pcie->msi;
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#endif
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hw.nr_controllers = 1;
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hw.private_data = (void **)&pcie;
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hw.setup = mvebu_pcie_setup;
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hw.map_irq = of_irq_parse_and_map_pci;
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hw.ops = &mvebu_pcie_ops;
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hw.align_resource = mvebu_pcie_align_resource;
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pci_common_init_dev(&pcie->pdev->dev, &hw);
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}
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/*
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* Looks up the list of register addresses encoded into the reg =
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* <...> property for one that matches the given port/lane. Once
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@ -1190,28 +1141,39 @@ static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
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clk_disable_unprepare(port->clk);
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}
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static int mvebu_pcie_probe(struct platform_device *pdev)
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/*
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* We can't use devm_of_pci_get_host_bridge_resources() because we
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* need to parse our special DT properties encoding the MEM and IO
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* apertures.
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*/
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static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
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{
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struct device *dev = &pdev->dev;
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struct mvebu_pcie *pcie;
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struct device *dev = &pcie->pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *child;
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int num, i, ret;
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unsigned int i;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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INIT_LIST_HEAD(&pcie->resources);
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pcie->pdev = pdev;
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platform_set_drvdata(pdev, pcie);
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/* Get the bus range */
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ret = of_pci_parse_bus_range(np, &pcie->busn);
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if (ret) {
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dev_err(dev, "failed to parse bus-range property: %d\n", ret);
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return ret;
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}
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pci_add_resource(&pcie->resources, &pcie->busn);
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/* Get the PCIe memory and I/O aperture */
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/* Get the PCIe memory aperture */
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mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
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if (resource_size(&pcie->mem) == 0) {
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dev_err(dev, "invalid memory aperture size\n");
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return -EINVAL;
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}
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pcie->mem.name = "PCI MEM";
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pci_add_resource(&pcie->resources, &pcie->mem);
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/* Get the PCIe IO aperture */
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mvebu_mbus_get_pcie_io_aperture(&pcie->io);
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if (resource_size(&pcie->io) != 0) {
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@ -1220,19 +1182,38 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
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pcie->realio.end = min_t(resource_size_t,
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IO_SPACE_LIMIT - SZ_64K,
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resource_size(&pcie->io) - 1);
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pcie->realio.name = "PCI I/O";
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for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
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pci_ioremap_io(i, pcie->io.start + i);
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} else
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pcie->realio = pcie->io;
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/* Get the bus range */
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ret = of_pci_parse_bus_range(np, &pcie->busn);
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if (ret) {
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dev_err(dev, "failed to parse bus-range property: %d\n", ret);
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return ret;
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pci_add_resource(&pcie->resources, &pcie->realio);
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}
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return devm_request_pci_bus_resources(dev, &pcie->resources);
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}
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static int mvebu_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mvebu_pcie *pcie;
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struct pci_host_bridge *bridge;
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struct device_node *np = dev->of_node;
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struct device_node *child;
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int num, i, ret;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
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if (!bridge)
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return -ENOMEM;
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pcie = pci_host_bridge_priv(bridge);
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pcie->pdev = pdev;
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platform_set_drvdata(pdev, pcie);
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ret = mvebu_pcie_parse_request_resources(pcie);
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if (ret)
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return ret;
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num = of_get_available_child_count(np);
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pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
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@ -1275,15 +1256,24 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
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continue;
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}
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mvebu_pcie_setup_hw(port);
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mvebu_pcie_set_local_dev_nr(port, 1);
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mvebu_sw_pci_bridge_init(port);
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}
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pcie->nports = i;
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mvebu_pcie_enable(pcie);
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list_splice_init(&pcie->resources, &bridge->windows);
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bridge->dev.parent = dev;
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bridge->sysdata = pcie;
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bridge->busnr = 0;
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bridge->ops = &mvebu_pcie_ops;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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bridge->align_resource = mvebu_pcie_align_resource;
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bridge->msi = pcie->msi;
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return 0;
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return pci_host_probe(bridge);
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}
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static const struct of_device_id mvebu_pcie_of_match_table[] = {
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