drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
No need to call the ->pre_pll_enable hook twice if we don't enable the dpll too early. This should make Jani a bit less grumpy. v2: Rebase on top of the newly-colored BUG_ONs. v3: Reinstate the lost write of the DPLL_MD register, spotted by Imre. Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1321,32 +1321,40 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
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assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
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}
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static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
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static void vlv_enable_pll(struct intel_crtc *crtc)
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{
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int reg;
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u32 val;
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int reg = DPLL(crtc->pipe);
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u32 dpll = crtc->config.dpll_hw_state.dpll;
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assert_pipe_disabled(dev_priv, pipe);
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assert_pipe_disabled(dev_priv, crtc->pipe);
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/* No really, not for ILK+ */
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BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
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/* PLL is protected by panel, make sure we can write it */
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if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
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assert_panel_unlocked(dev_priv, pipe);
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assert_panel_unlocked(dev_priv, crtc->pipe);
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reg = DPLL(pipe);
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val = I915_READ(reg);
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val |= DPLL_VCO_ENABLE;
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I915_WRITE(reg, dpll);
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POSTING_READ(reg);
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udelay(150);
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if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
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DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
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I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
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POSTING_READ(DPLL_MD(crtc->pipe));
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/* We do this three times for luck */
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I915_WRITE(reg, val);
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I915_WRITE(reg, dpll);
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POSTING_READ(reg);
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udelay(150); /* wait for warmup */
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I915_WRITE(reg, val);
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I915_WRITE(reg, dpll);
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POSTING_READ(reg);
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udelay(150); /* wait for warmup */
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I915_WRITE(reg, val);
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I915_WRITE(reg, dpll);
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POSTING_READ(reg);
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udelay(150); /* wait for warmup */
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}
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@ -3654,7 +3662,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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vlv_enable_pll(dev_priv, pipe);
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vlv_enable_pll(intel_crtc);
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for_each_encoder_on_crtc(dev, crtc, encoder)
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if (encoder->pre_enable)
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@ -4409,7 +4417,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_encoder *encoder;
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int pipe = crtc->pipe;
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u32 dpll, mdiv;
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u32 bestn, bestm1, bestm2, bestp1, bestp2;
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@ -4498,10 +4505,6 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
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for_each_encoder_on_crtc(dev, &crtc->base, encoder)
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if (encoder->pre_pll_enable)
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encoder->pre_pll_enable(encoder);
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/* Enable DPIO clock input */
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dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
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DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
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@ -4511,20 +4514,10 @@ static void vlv_update_pll(struct intel_crtc *crtc)
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dpll |= DPLL_VCO_ENABLE;
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crtc->config.dpll_hw_state.dpll = dpll;
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I915_WRITE(DPLL(pipe), dpll);
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POSTING_READ(DPLL(pipe));
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udelay(150);
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if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
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DRM_ERROR("DPLL %d failed to lock\n", pipe);
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dpll_md = (crtc->config.pixel_multiplier - 1)
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<< DPLL_MD_UDI_MULTIPLIER_SHIFT;
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crtc->config.dpll_hw_state.dpll_md = dpll_md;
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I915_WRITE(DPLL_MD(pipe), dpll_md);
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POSTING_READ(DPLL_MD(pipe));
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if (crtc->config.has_dp_encoder)
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intel_dp_set_m_n(crtc);
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