drm/nv20: Use the nv30 CRTC bandwidth calculation code.
nv2x CRTC FIFOs are as large as in nv3x (4kB it seems), and the FIFO control registers have the same layout: we can make them share the same implementation. Previously we were using the nv1x code, but the calculated FIFO watermarks are usually too low for nv2x and they cause horrible scanout artifacts. They've gone unnoticed until now because we've been leaving one of the bandwidth regs uninitialized (CRE 47, which contains the most significant bits of FFLWM), so everything seemed to work fine except in some cases after a cold boot, depending on the memory bandwidth and pixel clocks used. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -234,7 +234,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
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}
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static void
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nv30_update_arb(int *burst, int *lwm)
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nv20_update_arb(int *burst, int *lwm)
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{
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unsigned int fifo_size, burst_size, graphics_lwm;
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@ -251,14 +251,14 @@ nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->card_type < NV_30)
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if (dev_priv->card_type < NV_20)
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nv04_update_arb(dev, vclk, bpp, burst, lwm);
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else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
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(dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
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*burst = 128;
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*lwm = 0x0480;
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} else
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nv30_update_arb(burst, lwm);
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nv20_update_arb(burst, lwm);
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}
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static int
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@ -866,10 +866,11 @@ nv_save_state_ext(struct drm_device *dev, int head,
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rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
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if (dev_priv->card_type >= NV_30) {
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if (dev_priv->card_type >= NV_20)
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rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
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if (dev_priv->card_type >= NV_30)
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rd_cio_state(dev, head, regp, 0x9f);
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}
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rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
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rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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@ -976,10 +977,11 @@ nv_load_state_ext(struct drm_device *dev, int head,
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wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
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if (dev_priv->card_type >= NV_30) {
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if (dev_priv->card_type >= NV_20)
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wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
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if (dev_priv->card_type >= NV_30)
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wr_cio_state(dev, head, regp, 0x9f);
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}
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wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
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wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
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@ -826,7 +826,7 @@ nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
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if (dev_priv->card_type >= NV_30) {
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if (dev_priv->card_type >= NV_20) {
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regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
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crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
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}
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