[PATCH] mips: nuke trailing whitespace
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>hifive-unleashed-5.1
Ralf Baechle
Linus Torvalds
parent
875d43e72b
commit
42a3b4f25a
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@ -177,7 +177,7 @@ cflags-$(CONFIG_CPU_MIPS64) += \
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cflags-$(CONFIG_CPU_R5000) += \
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$(call set_gccflags,r5000,mips4,r5000,mips4,mips2) \
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-Wa,--trap
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-Wa,--trap
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cflags-$(CONFIG_CPU_R5432) += \
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$(call set_gccflags,r5400,mips4,r5000,mips4,mips2) \
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@ -720,7 +720,7 @@ archclean:
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@$(MAKE) $(clean)=arch/mips/boot
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@$(MAKE) $(clean)=arch/mips/lasat
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# Generate <asm/offset.h
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# Generate <asm/offset.h
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#
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# The default rule is suffering from funny problems on MIPS so we using our
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# own ...
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@ -40,14 +40,14 @@
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/* TBD */
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static struct resource pci_io_resource = {
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"pci IO space",
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"pci IO space",
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(u32)PCI_IO_START,
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(u32)PCI_IO_END,
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IORESOURCE_IO
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};
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static struct resource pci_mem_resource = {
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"pci memory space",
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"pci memory space",
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(u32)PCI_MEM_START,
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(u32)PCI_MEM_END,
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IORESOURCE_MEM
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@ -68,7 +68,7 @@ static unsigned long virt_io_addr;
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static int __init au1x_pci_setup(void)
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{
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
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virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
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virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
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Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
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if (!virt_io_addr) {
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@ -77,7 +77,7 @@ static int __init au1x_pci_setup(void)
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}
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#ifdef CONFIG_DMA_NONCOHERENT
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/*
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/*
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* Set the NC bit in controller for Au1500 pre-AC silicon
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*/
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u32 prid = read_c0_prid();
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@ -97,7 +97,7 @@ static int __init au1x00_setup(void)
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argptr = prom_getcmdline();
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strcat(argptr, " console=ttyS0,115200");
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}
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#endif
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#endif
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#ifdef CONFIG_FB_AU1100
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if ((argptr = strstr(argptr, "video=")) == NULL) {
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@ -281,7 +281,7 @@ unsigned long cal_r4koff(void)
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cpu_speed = count * 2;
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}
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#else
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
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AU1000_SRC_CLK;
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count = cpu_speed / 2;
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#endif
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@ -356,7 +356,7 @@ static unsigned long do_fast_cp0_gettimeoffset(void)
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: "hi", "lo", GCC_REG_ACCUM);
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/*
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* Due to possible jiffies inconsistencies, we need to check
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* Due to possible jiffies inconsistencies, we need to check
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* the result so that we'll get a timer that is monotonic.
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*/
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if (res >= USECS_PER_JIFFY)
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@ -375,8 +375,8 @@ static unsigned long do_fast_pm_gettimeoffset(void)
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au_sync();
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offset = pc0 - last_pc0;
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if (offset > 2*MATCH20_INC) {
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printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
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(unsigned)offset, (unsigned)last_pc0,
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printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
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(unsigned)offset, (unsigned)last_pc0,
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(unsigned)last_match20, (unsigned)pc0);
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}
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offset = (unsigned long)((offset * 305) / 10);
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@ -394,11 +394,11 @@ void au1xxx_timer_setup(struct irqaction *irq)
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r4k_offset = cal_r4koff();
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printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
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//est_freq = 2*r4k_offset*HZ;
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est_freq = r4k_offset*HZ;
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//est_freq = 2*r4k_offset*HZ;
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est_freq = r4k_offset*HZ;
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est_freq += 5000; /* round */
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est_freq -= est_freq%10000;
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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set_au1x00_speed(est_freq);
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set_au1x00_lcd_clock(); // program the LCD clock
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@ -182,7 +182,7 @@ void __init board_setup(void)
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au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
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au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
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au_writel(0x02a00356, Au1500_PCI_STATCMD);
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au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
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au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
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au_writel(0x00000008, Au1500_PCI_MBAR);
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au_sync();
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@ -216,7 +216,7 @@ csb250_pci_idsel(unsigned int devsel, int assert)
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unsigned int gpio2_pins;
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retval = 1;
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/* First, disable both selects, then assert the one requested.
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*/
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au_writel(0xc000c000, GPIO2_OUTPUT);
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@ -81,7 +81,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
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csb_env[0] = env1;
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mips_machgroup = MACH_GROUP_ALCHEMY;
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mips_machtype = MACH_CSB250;
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mips_machtype = MACH_CSB250;
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prom_init_cmdline();
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memsize_str = prom_getenv("memsize");
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@ -61,7 +61,7 @@ void __init prom_init(void)
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prom_envp = (char **) fw_arg2;
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mips_machgroup = MACH_GROUP_ALCHEMY;
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mips_machtype = MACH_DB1000; /* set the platform # */
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mips_machtype = MACH_DB1000; /* set the platform # */
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prom_init_cmdline();
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@ -63,7 +63,7 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
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prom_envp = envp;
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mips_machgroup = MACH_GROUP_ALCHEMY;
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mips_machtype = MACH_DB1000; /* set the platform # */
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mips_machtype = MACH_DB1000; /* set the platform # */
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prom_init_cmdline();
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memsize_str = prom_getenv("memsize");
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@ -174,7 +174,7 @@ void __init board_setup(void)
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case 0x02: /* HB */
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break;
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default: /* HC and newer */
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/* Enable sys bus clock divider when IDLE state or no bus
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/* Enable sys bus clock divider when IDLE state or no bus
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activity. */
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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break;
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@ -49,7 +49,7 @@ void board_reset (void)
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void __init board_setup(void)
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{
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u32 pin_func;
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// set multiple use pins (UART3/GPIO) to UART (it's used as UART too)
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pin_func = au_readl(SYS_PINFUNC) & (u32)(~SYS_PF_UR3);
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pin_func |= SYS_PF_UR3;
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@ -75,11 +75,11 @@ void __init board_setup(void)
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au_writel(1, GPIO2_ENABLE);
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/* gpio2 208/9/10/11 are inputs */
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au_writel((1<<8) | (1<<9) | (1<<10) | (1<<11), GPIO2_DIR);
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/* turn off power */
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au_writel((au_readl(GPIO2_PINSTATE) & ~(1<<14))|(1<<30), GPIO2_OUTPUT);
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#endif
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#ifdef CONFIG_PCI
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#if defined(__MIPSEB__)
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@ -55,7 +55,7 @@ void __init prom_init(void)
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prom_envp = (char **) fw_arg2;
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mips_machgroup = MACH_GROUP_ALCHEMY;
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mips_machtype = MACH_XXS1500; /* set the platform # */
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mips_machtype = MACH_XXS1500; /* set the platform # */
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prom_init_cmdline();
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@ -56,7 +56,7 @@ au1xxx_irq_map_t au1xxx_irq_map[] = {
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{ AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 },
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{ AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */
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@ -76,7 +76,7 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger)
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extern void vrc5477_irq_init(u32 base);
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extern void mips_cpu_irq_init(u32 base);
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extern asmlinkage void ddb5477_handle_int(void);
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
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static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
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void __init arch_init_irq(void)
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@ -94,7 +94,7 @@ void __init arch_init_irq(void)
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/* setup PCI interrupt attributes */
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set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
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set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
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if (mips_machtype == MACH_NEC_ROCKHOPPERII)
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if (mips_machtype == MACH_NEC_ROCKHOPPERII)
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set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
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else
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set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
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@ -134,7 +134,7 @@ void __init arch_init_irq(void)
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/* setup cascade interrupts */
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setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
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/* hook up the first-level interrupt handler */
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set_except_vector(0, ddb5477_handle_int);
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@ -141,7 +141,7 @@ static void __init ddb_time_init(void)
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/* mips_hpt_frequency is 1/2 of the cpu core freq */
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i = (read_c0_config() >> 28 ) & 7;
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if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
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if ((current_cpu_data.cputype == CPU_R5432) && (i == 3))
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i = 4;
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mips_hpt_frequency = bus_frequency*(i+4)/4;
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}
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@ -298,11 +298,11 @@ static void __init ddb5477_board_init(void)
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if (mips_machtype == MACH_NEC_ROCKHOPPER
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|| mips_machtype == MACH_NEC_ROCKHOPPERII) {
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/* Disable bus diagnostics. */
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/* Disable bus diagnostics. */
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ddb_out32(DDB_PCICTL0_L, 0);
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ddb_out32(DDB_PCICTL0_H, 0);
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ddb_out32(DDB_PCICTL1_L, 0);
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ddb_out32(DDB_PCICTL1_H, 0);
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ddb_out32(DDB_PCICTL1_H, 0);
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}
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if (mips_machtype == MACH_NEC_ROCKHOPPER) {
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@ -354,7 +354,7 @@ static void __init ddb5477_board_init(void)
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*/
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pci_write_config_byte(&dev_m1533, 0x58, 0x74);
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/*
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/*
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* positive decode (bit6 -0)
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* enable IDE controler interrupt (bit 4 -1)
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* setup SIRQ to point to IRQ 14 (bit 3:0 - 1101)
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@ -364,31 +364,31 @@ static void __init ddb5477_board_init(void)
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/* Setup M5229 registers */
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dev_m5229.bus = &bus;
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dev_m5229.sysdata = NULL;
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dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
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dev_m5229.devfn = 4*8; // slot 4 (AD15): M5229 IDE
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/*
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* enable IDE in the M5229 config register 0x50 (bit 0 - 1)
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* M5229 IDSEL is addr:15; see above setting
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* M5229 IDSEL is addr:15; see above setting
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*/
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pci_read_config_byte(&dev_m5229, 0x50, &temp8);
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pci_write_config_byte(&dev_m5229, 0x50, temp8 | 0x1);
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/*
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* enable bus master (bit 2) and IO decoding (bit 0)
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/*
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* enable bus master (bit 2) and IO decoding (bit 0)
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*/
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pci_read_config_byte(&dev_m5229, 0x04, &temp8);
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pci_write_config_byte(&dev_m5229, 0x04, temp8 | 0x5);
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/*
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* enable native, copied from arch/ppc/k2boot/head.S
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* TODO - need volatile, need to be portable
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* TODO - need volatile, need to be portable
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*/
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pci_write_config_byte(&dev_m5229, 0x09, 0xef);
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/* Set Primary Channel Command Block Timing */
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/* Set Primary Channel Command Block Timing */
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pci_write_config_byte(&dev_m5229, 0x59, 0x31);
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/*
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/*
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* Enable primary channel 40-pin cable
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* M5229 register 0x4a (bit 0)
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*/
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@ -253,7 +253,7 @@ static inline void dec_kn03_be_init(void)
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kn0x_erraddr = (void *)(KN03_SLOT_BASE + IOASIC_ERRADDR);
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kn0x_chksyn = (void *)(KN03_SLOT_BASE + IOASIC_CHKSYN);
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/*
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* Set normal ECC detection and generation, enable ECC correction.
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* For KN05 we also need to make sure EE (?) is enabled in the MB.
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@ -129,7 +129,7 @@ static void __init it8172_setup(void)
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/*
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* IO/MEM resources.
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*
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*
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* revisit this area.
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*/
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set_io_port_base(KSEG1);
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@ -72,7 +72,7 @@ static inline int rtc_dm_binary(void) { return saved_control & RTC_DM_BINARY; }
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static inline unsigned char
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bin_to_hw(unsigned char c)
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{
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if (rtc_dm_binary())
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if (rtc_dm_binary())
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return c;
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else
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return ((c/10) << 4) + (c%10);
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@ -91,9 +91,9 @@ hw_to_bin(unsigned char c)
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static inline unsigned char
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hour_bin_to_hw(unsigned char c)
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{
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if (rtc_24h())
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if (rtc_24h())
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return bin_to_hw(c);
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if (c >= 12)
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if (c >= 12)
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return 0x80 | bin_to_hw((c==12)?12:c-12); /* 12 is 12pm */
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else
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return bin_to_hw((c==0)?12:c); /* 0 is 12 AM, not 0 am */
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@ -105,9 +105,9 @@ hour_hw_to_bin(unsigned char c)
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unsigned char tmp = hw_to_bin(c&0x3f);
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if (rtc_24h())
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return tmp;
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if (c & 0x80)
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if (c & 0x80)
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return (tmp==12)?12:tmp+12; /* 12pm is 12, not 24 */
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else
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else
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return (tmp==12)?0:tmp; /* 12am is 0 */
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}
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@ -145,7 +145,7 @@ static unsigned long __init cal_r4koff(void)
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return (mips_hpt_frequency / HZ);
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}
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static unsigned long
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static unsigned long
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it8172_rtc_get_time(void)
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{
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unsigned int year, mon, day, hour, min, sec;
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@ -166,12 +166,12 @@ it8172_rtc_get_time(void)
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hour = hour_hw_to_bin(CMOS_READ(RTC_HOURS));
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day = hw_to_bin(CMOS_READ(RTC_DAY_OF_MONTH));
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mon = hw_to_bin(CMOS_READ(RTC_MONTH));
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year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
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year = hw_to_bin(CMOS_READ(RTC_YEAR)) +
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hw_to_bin(*rtc_century_reg) * 100;
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/* restore interrupts */
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local_irq_restore(flags);
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return mktime(year, mon, day, hour, min, sec);
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}
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@ -103,7 +103,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
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* Convert jiffies to nanoseconds and seperate with
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* one divide.
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*/
|
||||
u64 nsec = (u64)jiffies * TICK_NSEC;
|
||||
u64 nsec = (u64)jiffies * TICK_NSEC;
|
||||
value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
|
||||
value->tv_usec /= NSEC_PER_USEC;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
|
|||
* Convert jiffies to nanoseconds and seperate with
|
||||
* one divide.
|
||||
*/
|
||||
u64 nsec = (u64)jiffies * TICK_NSEC;
|
||||
u64 nsec = (u64)jiffies * TICK_NSEC;
|
||||
value->tv_sec = div_long_long_rem(nsec, NSEC_PER_SEC, &value->tv_usec);
|
||||
value->tv_usec /= NSEC_PER_USEC;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ static inline void check_mult_sh(void)
|
|||
for (i = 0; i < 8; i++)
|
||||
if (v1[i] != w[i])
|
||||
bug = 1;
|
||||
|
||||
|
||||
if (bug == 0) {
|
||||
printk("no.\n");
|
||||
return;
|
||||
|
|
@ -149,7 +149,7 @@ static inline void check_mult_sh(void)
|
|||
for (i = 0; i < 8; i++)
|
||||
if (v2[i] != w[i])
|
||||
fix = 0;
|
||||
|
||||
|
||||
if (fix == 1) {
|
||||
printk("yes.\n");
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -687,8 +687,8 @@ void handle_exception (struct gdb_regs *regs)
|
|||
* acquire the big kgdb spinlock
|
||||
*/
|
||||
if (!spin_trylock(&kgdb_lock)) {
|
||||
/*
|
||||
* some other CPU has the lock, we should go back to
|
||||
/*
|
||||
* some other CPU has the lock, we should go back to
|
||||
* receive the gdb_wait IPC
|
||||
*/
|
||||
return;
|
||||
|
|
@ -703,7 +703,7 @@ void handle_exception (struct gdb_regs *regs)
|
|||
async_bp.addr = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* acquire the CPU spinlocks
|
||||
*/
|
||||
for (i = num_online_cpus()-1; i >= 0; i--)
|
||||
|
|
@ -894,7 +894,7 @@ void handle_exception (struct gdb_regs *regs)
|
|||
ptr = &input_buffer[1];
|
||||
if (hexToLong(&ptr, &addr))
|
||||
regs->cp0_epc = addr;
|
||||
|
||||
|
||||
goto exit_kgdb_exception;
|
||||
break;
|
||||
|
||||
|
|
@ -1001,7 +1001,7 @@ void breakpoint(void)
|
|||
return;
|
||||
|
||||
__asm__ __volatile__(
|
||||
".globl breakinst\n\t"
|
||||
".globl breakinst\n\t"
|
||||
".set\tnoreorder\n\t"
|
||||
"nop\n"
|
||||
"breakinst:\tbreak\n\t"
|
||||
|
|
@ -1014,7 +1014,7 @@ void breakpoint(void)
|
|||
void async_breakpoint(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".globl async_breakinst\n\t"
|
||||
".globl async_breakinst\n\t"
|
||||
".set\tnoreorder\n\t"
|
||||
"nop\n"
|
||||
"async_breakinst:\tbreak\n\t"
|
||||
|
|
|
|||
|
|
@ -246,10 +246,10 @@ NESTED(nmi_handler, PT_SIZE, sp)
|
|||
LONG_L a1, PT_EPC(sp)
|
||||
#if CONFIG_32BIT
|
||||
PRINT("Got \nexception at %08lx\012")
|
||||
#endif
|
||||
#endif
|
||||
#if CONFIG_64BIT
|
||||
PRINT("Got \nexception at %016lx\012")
|
||||
#endif
|
||||
#endif
|
||||
.endm
|
||||
|
||||
.macro __BUILD_count exception
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ long sys_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
|
|||
#include "compat_ioctl.c"
|
||||
|
||||
typedef int (* ioctl32_handler_t)(unsigned int, unsigned int, unsigned long, struct file *);
|
||||
|
||||
|
||||
#define COMPATIBLE_IOCTL(cmd) HANDLE_IOCTL((cmd),sys_ioctl)
|
||||
#define HANDLE_IOCTL(cmd,handler) { (cmd), (ioctl32_handler_t)(handler), NULL },
|
||||
#define IOCTL_TABLE_START \
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ int show_interrupts(struct seq_file *p, void *v)
|
|||
if (i < NR_IRQS) {
|
||||
spin_lock_irqsave(&irq_desc[i].lock, flags);
|
||||
action = irq_desc[i].action;
|
||||
if (!action)
|
||||
if (!action)
|
||||
goto skip;
|
||||
seq_printf(p, "%3d: ",i);
|
||||
#ifndef CONFIG_SMP
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@ asmlinkage int sys32_sysinfo(struct sysinfo32 *info)
|
|||
struct sysinfo s;
|
||||
int ret, err;
|
||||
mm_segment_t old_fs = get_fs ();
|
||||
|
||||
|
||||
set_fs (KERNEL_DS);
|
||||
ret = sys_sysinfo(&s);
|
||||
set_fs (old_fs);
|
||||
|
|
@ -560,7 +560,7 @@ struct ipc64_perm32 {
|
|||
compat_gid_t gid;
|
||||
compat_uid_t cuid;
|
||||
compat_gid_t cgid;
|
||||
compat_mode_t mode;
|
||||
compat_mode_t mode;
|
||||
unsigned short seq;
|
||||
unsigned short __pad1;
|
||||
unsigned int __unused1;
|
||||
|
|
@ -1334,17 +1334,17 @@ asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t *offset,
|
|||
mm_segment_t old_fs = get_fs();
|
||||
int ret;
|
||||
off_t of;
|
||||
|
||||
|
||||
if (offset && get_user(of, offset))
|
||||
return -EFAULT;
|
||||
|
||||
|
||||
set_fs(KERNEL_DS);
|
||||
ret = sys_sendfile(out_fd, in_fd, offset ? &of : NULL, count);
|
||||
set_fs(old_fs);
|
||||
|
||||
|
||||
if (offset && put_user(of, offset))
|
||||
return -EFAULT;
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1362,11 +1362,11 @@ static unsigned char socketcall_nargs[18]={AL(0),AL(3),AL(3),AL(3),AL(2),AL(3),
|
|||
#undef AL
|
||||
|
||||
/*
|
||||
* System call vectors.
|
||||
* System call vectors.
|
||||
*
|
||||
* Argument checking cleaned up. Saved 20% in size.
|
||||
* This function doesn't need to set the kernel lock because
|
||||
* it is set by the callees.
|
||||
* it is set by the callees.
|
||||
*/
|
||||
|
||||
asmlinkage long sys32_socketcall(int call, unsigned int *args32)
|
||||
|
|
@ -1402,11 +1402,11 @@ asmlinkage long sys32_socketcall(int call, unsigned int *args32)
|
|||
/* copy_from_user should be SMP safe. */
|
||||
if (copy_from_user(a, args32, socketcall_nargs[call]))
|
||||
return -EFAULT;
|
||||
|
||||
|
||||
a0=a[0];
|
||||
a1=a[1];
|
||||
|
||||
switch(call)
|
||||
|
||||
switch(call)
|
||||
{
|
||||
case SYS_SOCKET:
|
||||
err = sys_socket(a0,a1,a[2]);
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
/*
|
||||
* FPU context is saved iff the process has used it's FPU in the current
|
||||
* time slice as indicated by TIF_USEDFPU. In any case, the CU1 bit for user
|
||||
* space STATUS register should be 0, so that a process *always* starts its
|
||||
* space STATUS register should be 0, so that a process *always* starts its
|
||||
* userland with FPU disabled after each context switch.
|
||||
*
|
||||
* FPU will be enabled as soon as the process accesses FPU again, through
|
||||
|
|
@ -55,7 +55,7 @@ LEAF(resume)
|
|||
cpu_save_nonscratch a0
|
||||
sw ra, THREAD_REG31(a0)
|
||||
|
||||
/*
|
||||
/*
|
||||
* check if we need to save FPU registers
|
||||
*/
|
||||
lw t3, TASK_THREAD_INFO(a0)
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
/*
|
||||
* FPU context is saved iff the process has used it's FPU in the current
|
||||
* time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
|
||||
* space STATUS register should be 0, so that a process *always* starts its
|
||||
* space STATUS register should be 0, so that a process *always* starts its
|
||||
* userland with FPU disabled after each context switch.
|
||||
*
|
||||
* FPU will be enabled as soon as the process accesses FPU again, through
|
||||
|
|
@ -164,7 +164,7 @@ LEAF(_init_fpu)
|
|||
dmtc1 t1, $f31
|
||||
1:
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_MIPS32
|
||||
mtc1 t1, $f0
|
||||
mtc1 t1, $f1
|
||||
|
|
|
|||
|
|
@ -558,7 +558,7 @@ static inline int setup_sigcontext32(struct pt_regs *regs,
|
|||
if (!used_math())
|
||||
goto out;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Save FPU state to signal context. Signal handler will "inherit"
|
||||
* current FPU state.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ SECTIONS
|
|||
/* This is the value for an Origin kernel, taken from an IRIX kernel. */
|
||||
/* . = 0xc00000000001c000; */
|
||||
|
||||
/* Set the vaddr for the text segment to a value
|
||||
/* Set the vaddr for the text segment to a value
|
||||
>= 0xa800 0000 0001 9000 if no symmon is going to configured
|
||||
>= 0xa800 0000 0030 0000 otherwise */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
/*
|
||||
* Atmel AT93C46 serial eeprom driver
|
||||
*
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -21,12 +21,12 @@
|
|||
|
||||
struct at93c_defs *at93c;
|
||||
|
||||
static void at93c_reg_write(u32 val)
|
||||
static void at93c_reg_write(u32 val)
|
||||
{
|
||||
*at93c->reg = val;
|
||||
}
|
||||
|
||||
static u32 at93c_reg_read(void)
|
||||
static u32 at93c_reg_read(void)
|
||||
{
|
||||
u32 tmp = *at93c->reg;
|
||||
return tmp;
|
||||
|
|
@ -81,7 +81,7 @@ static u8 at93c_read_byte(void)
|
|||
}
|
||||
|
||||
static void at93c_write_bits(u32 data, int size)
|
||||
{
|
||||
{
|
||||
int i;
|
||||
int shift = size - 1;
|
||||
u32 mask = (1 << shift);
|
||||
|
|
@ -90,7 +90,7 @@ static void at93c_write_bits(u32 data, int size)
|
|||
at93c_write_databit((data & mask) >> shift);
|
||||
data <<= 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void at93c_init_op(void)
|
||||
{
|
||||
|
|
@ -104,8 +104,8 @@ static void at93c_end_op(void)
|
|||
lasat_ndelay(250);
|
||||
}
|
||||
|
||||
static void at93c_wait(void)
|
||||
{
|
||||
static void at93c_wait(void)
|
||||
{
|
||||
at93c_init_op();
|
||||
while (!at93c_read_databit())
|
||||
;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
/*
|
||||
* Atmel AT93C46 serial eeprom driver
|
||||
*
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Dallas Semiconductors 1603 RTC driver
|
||||
/*
|
||||
* Dallas Semiconductors 1603 RTC driver
|
||||
*
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -20,12 +20,12 @@
|
|||
struct ds_defs *ds1603 = NULL;
|
||||
|
||||
/* HW specific register functions */
|
||||
static void rtc_reg_write(unsigned long val)
|
||||
static void rtc_reg_write(unsigned long val)
|
||||
{
|
||||
*ds1603->reg = val;
|
||||
}
|
||||
|
||||
static unsigned long rtc_reg_read(void)
|
||||
static unsigned long rtc_reg_read(void)
|
||||
{
|
||||
unsigned long tmp = *ds1603->reg;
|
||||
return tmp;
|
||||
|
|
@ -80,7 +80,7 @@ static unsigned int rtc_read_databit(void)
|
|||
{
|
||||
unsigned int data;
|
||||
|
||||
data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
|
||||
data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
|
||||
>> ds1603->data_read_shift;
|
||||
rtc_cycle_clock(rtc_reg_read());
|
||||
return data;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Dallas Semiconductors 1603 RTC driver
|
||||
/*
|
||||
* Dallas Semiconductors 1603 RTC driver
|
||||
*
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
*
|
||||
*/
|
||||
#ifndef __DS1603_H
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ LDSCRIPT= -L$(obj) -Tromscript.normal
|
|||
HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
|
||||
-D_kernel_entry=0x$(KERNEL_ENTRY) \
|
||||
-D VERSION="\"$(Version)\"" \
|
||||
-D TIMESTAMP=$(shell date +%s)
|
||||
-D TIMESTAMP=$(shell date +%s)
|
||||
|
||||
$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
|
||||
$(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
|
||||
|
|
|
|||
|
|
@ -27,5 +27,5 @@ reldate:
|
|||
.word TIMESTAMP
|
||||
|
||||
.org 0x50
|
||||
release:
|
||||
release:
|
||||
.string VERSION
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* Routines for generic manipulation of the interrupts found on the
|
||||
* Routines for generic manipulation of the interrupts found on the
|
||||
* Lasat boards.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
|
|
@ -101,7 +101,7 @@ static unsigned long get_int_status_100(void)
|
|||
return *lasat_int_status & *lasat_int_mask;
|
||||
}
|
||||
|
||||
static unsigned long get_int_status_200(void)
|
||||
static unsigned long get_int_status_200(void)
|
||||
{
|
||||
unsigned long int_status;
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static void init_flash_sizes(void)
|
|||
|
||||
if (mips_machtype == MACH_LASAT_100) {
|
||||
lasat_board_info.li_flash_base = 0x1e000000;
|
||||
|
||||
|
||||
lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
|
||||
|
||||
if (lasat_board_info.li_flash_size > 0x200000) {
|
||||
|
|
@ -103,7 +103,7 @@ int lasat_init_board_info(void)
|
|||
memset(&lasat_board_info, 0, sizeof(lasat_board_info));
|
||||
|
||||
/* First read the EEPROM info */
|
||||
EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
|
||||
EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
|
||||
sizeof(struct lasat_eeprom_struct));
|
||||
|
||||
/* Check the CRC */
|
||||
|
|
@ -188,7 +188,7 @@ int lasat_init_board_info(void)
|
|||
case 0x1:
|
||||
lasat_board_info.li_cpu_hz =
|
||||
lasat_board_info.li_bus_hz +
|
||||
(lasat_board_info.li_bus_hz >> 1);
|
||||
(lasat_board_info.li_bus_hz >> 1);
|
||||
break;
|
||||
case 0x2:
|
||||
lasat_board_info.li_cpu_hz =
|
||||
|
|
@ -271,7 +271,7 @@ void lasat_write_eeprom_info(void)
|
|||
lasat_board_info.li_eeprom_info.crc32 = crc;
|
||||
|
||||
/* Write the EEPROM info */
|
||||
EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
|
||||
EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
|
||||
sizeof(struct lasat_eeprom_struct));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
/*
|
||||
* Picvue PVC160206 display driver
|
||||
*
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
* Brian Murphy <brian@murphy.dk>
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -24,12 +24,12 @@ struct pvc_defs *picvue = NULL;
|
|||
|
||||
DECLARE_MUTEX(pvc_sem);
|
||||
|
||||
static void pvc_reg_write(u32 val)
|
||||
static void pvc_reg_write(u32 val)
|
||||
{
|
||||
*picvue->reg = val;
|
||||
}
|
||||
|
||||
static u32 pvc_reg_read(void)
|
||||
static u32 pvc_reg_read(void)
|
||||
{
|
||||
u32 tmp = *picvue->reg;
|
||||
return tmp;
|
||||
|
|
@ -65,12 +65,12 @@ static u8 pvc_read_data(void)
|
|||
{
|
||||
u32 data = pvc_reg_read();
|
||||
u8 byte;
|
||||
data |= picvue->rw;
|
||||
data |= picvue->rw;
|
||||
data &= ~picvue->rs;
|
||||
pvc_reg_write(data);
|
||||
ndelay(40);
|
||||
byte = pvc_read_byte(data);
|
||||
data |= picvue->rs;
|
||||
data |= picvue->rs;
|
||||
pvc_reg_write(data);
|
||||
return byte;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
/*
|
||||
* Picvue PVC160206 display driver
|
||||
*
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
*
|
||||
*/
|
||||
#include <asm/semaphore.h>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
/*
|
||||
* Picvue PVC160206 display driver
|
||||
*
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
* Brian Murphy <brian.murphy@eicon.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
|
@ -51,10 +51,10 @@ static int pvc_proc_read_line(char *page, char **start,
|
|||
page += sprintf(page, "%s\n", pvc_lines[lineno]);
|
||||
up(&pvc_sem);
|
||||
|
||||
return page - origpage;
|
||||
return page - origpage;
|
||||
}
|
||||
|
||||
static int pvc_proc_write_line(struct file *file, const char *buffer,
|
||||
static int pvc_proc_write_line(struct file *file, const char *buffer,
|
||||
unsigned long count, void *data)
|
||||
{
|
||||
int origcount = count;
|
||||
|
|
@ -119,7 +119,7 @@ static int pvc_proc_read_scroll(char *page, char **start,
|
|||
page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
|
||||
up(&pvc_sem);
|
||||
|
||||
return page - origpage;
|
||||
return page - origpage;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static void null_prom_putc(char c)
|
|||
/* these are functions provided by the bootloader */
|
||||
static void (* prom_putc)(char c) = null_prom_putc;
|
||||
void (* prom_printf)(const char * fmt, ...) = null_prom_printf;
|
||||
void (* prom_display)(const char *string, int pos, int clear) =
|
||||
void (* prom_display)(const char *string, int pos, int clear) =
|
||||
null_prom_display;
|
||||
void (* prom_monitor)(void) = null_prom_monitor;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/*
|
||||
/*
|
||||
* Thomas Horsten <thh@lasat.com>
|
||||
* Copyright (C) 2000 LASAT Networks A/S.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -105,7 +105,7 @@ static int lasat_panic_prom_monitor(struct notifier_block *this,
|
|||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block lasat_panic_block[] =
|
||||
static struct notifier_block lasat_panic_block[] =
|
||||
{
|
||||
{ lasat_panic_display, NULL, INT_MAX },
|
||||
{ lasat_panic_prom_monitor, NULL, INT_MIN }
|
||||
|
|
@ -120,7 +120,7 @@ static void lasat_timer_setup(struct irqaction *irq)
|
|||
{
|
||||
|
||||
write_c0_compare(
|
||||
read_c0_count() +
|
||||
read_c0_count() +
|
||||
mips_hpt_frequency / HZ);
|
||||
change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,14 +37,14 @@
|
|||
|
||||
static DECLARE_MUTEX(lasat_info_sem);
|
||||
|
||||
/* Strategy function to write EEPROM after changing string entry */
|
||||
/* Strategy function to write EEPROM after changing string entry */
|
||||
int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
|
||||
void *oldval, size_t *oldlenp,
|
||||
void *newval, size_t newlen, void **context)
|
||||
{
|
||||
int r;
|
||||
down(&lasat_info_sem);
|
||||
r = sysctl_string(table, name,
|
||||
r = sysctl_string(table, name,
|
||||
nlen, oldval, oldlenp, newval, newlen, context);
|
||||
if (r < 0) {
|
||||
up(&lasat_info_sem);
|
||||
|
|
@ -74,7 +74,7 @@ int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* proc function to write EEPROM after changing int entry */
|
||||
/* proc function to write EEPROM after changing int entry */
|
||||
int proc_dolasatint(ctl_table *table, int write, struct file *filp,
|
||||
void *buffer, size_t *lenp, loff_t *ppos)
|
||||
{
|
||||
|
|
@ -93,7 +93,7 @@ int proc_dolasatint(ctl_table *table, int write, struct file *filp,
|
|||
static int rtctmp;
|
||||
|
||||
#ifdef CONFIG_DS1603
|
||||
/* proc function to read/write RealTime Clock */
|
||||
/* proc function to read/write RealTime Clock */
|
||||
int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
|
||||
void *buffer, size_t *lenp, loff_t *ppos)
|
||||
{
|
||||
|
|
@ -165,9 +165,9 @@ static char lasat_bcastaddr[16];
|
|||
void update_bcastaddr(void)
|
||||
{
|
||||
unsigned int ip;
|
||||
|
||||
ip = (lasat_board_info.li_eeprom_info.ipaddr &
|
||||
lasat_board_info.li_eeprom_info.netmask) |
|
||||
|
||||
ip = (lasat_board_info.li_eeprom_info.ipaddr &
|
||||
lasat_board_info.li_eeprom_info.netmask) |
|
||||
~lasat_board_info.li_eeprom_info.netmask;
|
||||
|
||||
sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
|
||||
|
|
@ -205,7 +205,7 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
|
|||
break;
|
||||
len++;
|
||||
}
|
||||
if (len >= sizeof(proc_lasat_ipbuf)-1)
|
||||
if (len >= sizeof(proc_lasat_ipbuf)-1)
|
||||
len = sizeof(proc_lasat_ipbuf) - 1;
|
||||
if (copy_from_user(proc_lasat_ipbuf, buffer, len))
|
||||
{
|
||||
|
|
@ -249,8 +249,8 @@ int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
|
|||
}
|
||||
#endif /* defined(CONFIG_INET) */
|
||||
|
||||
static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
|
||||
void *oldval, size_t *oldlenp,
|
||||
static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
|
||||
void *oldval, size_t *oldlenp,
|
||||
void *newval, size_t newlen,
|
||||
void **context)
|
||||
{
|
||||
|
|
@ -293,7 +293,7 @@ int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
|
|||
if (!strcmp(filp->f_dentry->d_name.name, "debugaccess"))
|
||||
lasat_board_info.li_eeprom_info.debugaccess = lasat_board_info.li_debugaccess;
|
||||
}
|
||||
lasat_write_eeprom_info();
|
||||
lasat_write_eeprom_info();
|
||||
up(&lasat_info_sem);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -316,8 +316,8 @@ static ctl_table lasat_table[] = {
|
|||
0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
|
||||
{LASAT_NETMASK, "netmask", &lasat_board_info.li_eeprom_info.netmask, sizeof(int),
|
||||
0644, NULL, &proc_lasat_ip, &sysctl_lasat_intvec},
|
||||
{LASAT_BCAST, "bcastaddr", &lasat_bcastaddr,
|
||||
sizeof(lasat_bcastaddr), 0600, NULL,
|
||||
{LASAT_BCAST, "bcastaddr", &lasat_bcastaddr,
|
||||
sizeof(lasat_bcastaddr), 0600, NULL,
|
||||
&proc_dostring, &sysctl_string},
|
||||
#endif
|
||||
{LASAT_PASSWORD, "passwd_hash", &lasat_board_info.li_eeprom_info.passwd_hash, sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for MIPS-specific library files..
|
||||
#
|
||||
|
||||
lib-y += csum_partial.o memset.o watch.o
|
||||
lib-y += csum_partial.o memset.o watch.o
|
||||
|
||||
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
|
||||
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for MIPS-specific library files..
|
||||
#
|
||||
|
||||
lib-y += csum_partial.o memset.o watch.o
|
||||
lib-y += csum_partial.o memset.o watch.o
|
||||
|
||||
obj-$(CONFIG_CPU_MIPS32) += dump_tlb.o
|
||||
obj-$(CONFIG_CPU_MIPS64) += dump_tlb.o
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@
|
|||
#define NBYTES 8
|
||||
#define LOG_NBYTES 3
|
||||
|
||||
/*
|
||||
/*
|
||||
* As we are sharing code base with the mips32 tree (which use the o32 ABI
|
||||
* register definitions). We need to redefine the register definitions from
|
||||
* the n64 ABI register naming to the o32 ABI register naming.
|
||||
|
|
@ -118,7 +118,7 @@
|
|||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
|
||||
|
||||
#else
|
||||
|
||||
#define LOAD lw
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ void __init arch_init_irq(void)
|
|||
int i;
|
||||
|
||||
atlas_hw0_icregs = (struct atlas_ictrl_regs *)ioremap (ATLAS_ICTRL_REGS_BASE, sizeof(struct atlas_ictrl_regs *));
|
||||
|
||||
|
||||
/*
|
||||
* Mask out all interrupt by writing "1" to all bit position in
|
||||
* the interrupt reset reg.
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ void __init kgdb_config (void)
|
|||
generic_putDebugChar = saa9730_putDebugChar;
|
||||
generic_getDebugChar = saa9730_getDebugChar;
|
||||
}
|
||||
else
|
||||
else
|
||||
#endif
|
||||
{
|
||||
speed = rs_kgdb_hook(line, speed);
|
||||
|
|
@ -243,7 +243,7 @@ void __init prom_init(void)
|
|||
mips_revision_corid = MIPS_REVISION_CORID;
|
||||
|
||||
if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
|
||||
if (BONITO_PCIDID == 0x0001df53 ||
|
||||
if (BONITO_PCIDID == 0x0001df53 ||
|
||||
BONITO_PCIDID == 0x0003df53)
|
||||
mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
|
||||
else
|
||||
|
|
@ -310,7 +310,7 @@ void __init prom_init(void)
|
|||
case MIPS_REVISION_CORID_CORE_MSC:
|
||||
case MIPS_REVISION_CORID_CORE_FPGA2:
|
||||
case MIPS_REVISION_CORID_CORE_EMUL_MSC:
|
||||
_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
|
||||
_pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
|
||||
|
||||
#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
||||
MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ static unsigned int __init estimate_cpu_frequency(void)
|
|||
* really calculate the timer frequency
|
||||
* For now we hardwire the SEAD board frequency to 12MHz.
|
||||
*/
|
||||
|
||||
|
||||
if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
|
||||
(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
|
||||
count = 12000000;
|
||||
|
|
|
|||
|
|
@ -149,15 +149,15 @@ static int __init malta_setup(void)
|
|||
argptr = prom_getcmdline();
|
||||
if (strstr(argptr, "iobcuncached")) {
|
||||
BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
|
||||
BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
|
||||
BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
|
||||
~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
|
||||
BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
|
||||
printk("Disabled Bonito IOBC coherency\n");
|
||||
}
|
||||
else {
|
||||
BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
|
||||
BONITO_PCIMEMBASECFG |=
|
||||
(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
|
||||
BONITO_PCIMEMBASECFG |=
|
||||
(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
|
||||
BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
|
||||
printk("Disabled Bonito IOBC coherency\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -126,13 +126,13 @@ static inline void tx49_blast_icache32(void)
|
|||
|
||||
CACHE32_UNROLL32_ALIGN2;
|
||||
/* I'm in even chunk. blast odd chunks */
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
|
||||
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
||||
CACHE32_UNROLL32_ALIGN;
|
||||
/* I'm in odd chunk. blast even chunks */
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start; addr < end; addr += 0x400 * 2)
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start; addr < end; addr += 0x400 * 2)
|
||||
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
||||
}
|
||||
|
||||
|
|
@ -156,13 +156,13 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
|
|||
|
||||
CACHE32_UNROLL32_ALIGN2;
|
||||
/* I'm in even chunk. blast odd chunks */
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
|
||||
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
||||
CACHE32_UNROLL32_ALIGN;
|
||||
/* I'm in odd chunk. blast even chunks */
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start; addr < end; addr += 0x400 * 2)
|
||||
for (ws = 0; ws < ws_end; ws += ws_inc)
|
||||
for (addr = start; addr < end; addr += 0x400 * 2)
|
||||
cache32_unroll32(addr|ws,Index_Invalidate_I);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -270,7 +270,7 @@ static void local_sb1_flush_icache_range(unsigned long start,
|
|||
__sb1_writeback_inv_dcache_all();
|
||||
else
|
||||
__sb1_writeback_inv_dcache_range(start, end);
|
||||
|
||||
|
||||
/* Just flush the whole icache if the range is big enough */
|
||||
if ((end - start) > icache_range_cutoff)
|
||||
__sb1_flush_icache_all();
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
#include <asm/sibyte/sb1250_regs.h>
|
||||
#include <asm/sibyte/sb1250_scd.h>
|
||||
#endif
|
||||
|
||||
|
||||
/* SB1 definitions */
|
||||
|
||||
/* XXX should come from config1 XXX */
|
||||
|
|
@ -136,14 +136,14 @@ static inline void breakout_cerrd(unsigned int val)
|
|||
|
||||
#ifndef CONFIG_SIBYTE_BUS_WATCHER
|
||||
|
||||
static void check_bus_watcher(void)
|
||||
{
|
||||
static void check_bus_watcher(void)
|
||||
{
|
||||
uint32_t status, l2_err, memio_err;
|
||||
|
||||
/* Destructive read, clears register and interrupt */
|
||||
status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
|
||||
/* Bit 31 is always on, but there's no #define for that */
|
||||
if (status & ~(1UL << 31)) {
|
||||
if (status & ~(1UL << 31)) {
|
||||
l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
|
||||
memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
|
||||
prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
|
||||
|
|
@ -153,14 +153,14 @@ static void check_bus_watcher(void)
|
|||
(int)(G_SCD_BERR_TID(status) >> 6),
|
||||
(int)G_SCD_BERR_RID(status),
|
||||
(int)G_SCD_BERR_DCODE(status));
|
||||
} else {
|
||||
prom_printf("Bus watcher indicates no error\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
extern void check_bus_watcher(void);
|
||||
#endif
|
||||
|
||||
} else {
|
||||
prom_printf("Bus watcher indicates no error\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
extern void check_bus_watcher(void);
|
||||
#endif
|
||||
|
||||
asmlinkage void sb1_cache_error(void)
|
||||
{
|
||||
uint64_t cerr_dpa;
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|||
|
||||
for (i = 0; i < nents; i++, sg++) {
|
||||
unsigned long addr;
|
||||
|
||||
|
||||
addr = (unsigned long) page_address(sg->page);
|
||||
if (addr)
|
||||
__dma_sync(addr + sg->offset, sg->length, direction);
|
||||
|
|
@ -230,9 +230,9 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
|
|||
size_t size, enum dma_data_direction direction)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
||||
|
||||
addr = dma_handle + PAGE_OFFSET;
|
||||
__dma_sync(addr, size, direction);
|
||||
}
|
||||
|
|
@ -282,9 +282,9 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
|
|||
enum dma_data_direction direction)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
||||
BUG_ON(direction == DMA_NONE);
|
||||
|
||||
|
||||
/* Make sure that gcc doesn't leave the empty loop body. */
|
||||
for (i = 0; i < nelems; i++, sg++)
|
||||
__dma_sync((unsigned long)page_address(sg->page),
|
||||
|
|
|
|||
|
|
@ -198,7 +198,7 @@ static inline void copy_page_cpu(void *to, void *from)
|
|||
|
||||
/*
|
||||
* Pad descriptors to cacheline, since each is exclusively owned by a
|
||||
* particular CPU.
|
||||
* particular CPU.
|
||||
*/
|
||||
typedef struct dmadscr_s {
|
||||
u64 dscr_a;
|
||||
|
|
|
|||
|
|
@ -27,11 +27,11 @@
|
|||
SAVE_ALL
|
||||
CLI
|
||||
.set at
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t2, CP0_STATUS
|
||||
|
||||
and t0, t2
|
||||
|
||||
|
||||
andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
|
||||
bnez t1, ll_sw0_irq
|
||||
andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
|
||||
|
|
@ -103,25 +103,25 @@ ll_pcia_irq:
|
|||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
ll_pcib_irq:
|
||||
li a0, 5
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
ll_uart_irq:
|
||||
li a0, 6
|
||||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
ll_cputimer_irq:
|
||||
li a0, 7
|
||||
move a1, sp
|
||||
jal ll_timer_interrupt
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
ll_mv64340_decode_irq:
|
||||
move a0, sp
|
||||
jal ll_mv64340_irq
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ static u8 exchange_bit(u8 val, u8 cs)
|
|||
|
||||
/* turn the clock off and read-strobe */
|
||||
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
|
||||
|
||||
|
||||
/* return the data */
|
||||
return ((JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -451,7 +451,7 @@ static int __init momenco_jaguar_atx_setup(void)
|
|||
#ifdef GEMDEBUG_TRACEBUFFER
|
||||
{
|
||||
unsigned int tbControl;
|
||||
tbControl =
|
||||
tbControl =
|
||||
0 << 26 | /* post trigger delay 0 */
|
||||
0x2 << 16 | /* sequential trace mode */
|
||||
// 0x0 << 16 | /* non-sequential trace mode */
|
||||
|
|
|
|||
|
|
@ -27,11 +27,11 @@
|
|||
SAVE_ALL
|
||||
CLI
|
||||
.set at
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t2, CP0_STATUS
|
||||
|
||||
and t0, t2
|
||||
|
||||
|
||||
andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
|
||||
bnez t1, ll_sw0_irq
|
||||
andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
|
||||
|
|
@ -83,7 +83,7 @@ ll_pmc_irq:
|
|||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
ll_cpci_decode_irq:
|
||||
move a0, sp
|
||||
jal ll_cpci_irq
|
||||
|
|
@ -99,4 +99,4 @@ ll_cputimer_irq:
|
|||
move a1, sp
|
||||
jal do_IRQ
|
||||
j ret_from_irq
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static u8 exchange_bit(u8 val, u8 cs)
|
|||
|
||||
/* turn the clock off and read-strobe */
|
||||
OCELOT_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
|
||||
|
||||
|
||||
/* return the data */
|
||||
return ((OCELOT_FPGA_READ(EEPROM_MODE) >> 3) & 0x1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ static void ddb5074_fixup(struct pci_dev *dev)
|
|||
{
|
||||
extern struct pci_dev *pci_pmu;
|
||||
u8 t8;
|
||||
|
||||
|
||||
pci_pmu = dev; /* for LEDs D2 and D3 */
|
||||
/* Program the lines for LEDs D2 and D3 to output */
|
||||
pci_read_config_byte(dev, 0x7d, &t8);
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ static void ddb5477_amd_lance_fixup(struct pci_dev *dev)
|
|||
ioaddr = pci_resource_start(dev, 0);
|
||||
|
||||
inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */
|
||||
|
||||
|
||||
/* bcr_18 |= 0x0800 */
|
||||
outw(18, ioaddr + PCNET32_WIO_RAP);
|
||||
temp = inw(ioaddr + PCNET32_WIO_BDP);
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
|
|||
0, 0, 0, 3,
|
||||
4, 5, 6, 7,
|
||||
0, 9, 10, 11,
|
||||
12, 0, 14, 15
|
||||
12, 0, 14, 15
|
||||
};
|
||||
int i;
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* Copyright (C) 2004 MontaVista Software Inc.
|
||||
* Author: Manish Lachwani (mlachwani@mvista.com)
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
* Device 4: Unused
|
||||
* Device 5: Slot 2
|
||||
* Device 6: Slot 3
|
||||
* Device 7: Slot 4
|
||||
* Device 7: Slot 4
|
||||
*
|
||||
* Documentation says the VGA is device 5 and device 3 is unused but that
|
||||
* seem to be a documentation error. At least on my RM200C the Cirrus
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static inline void ddb_close_config_base(struct pci_config_swap *swap)
|
|||
}
|
||||
|
||||
static int read_config_dword(struct pci_config_swap *swap,
|
||||
struct pci_bus *bus, u32 devfn, u32 where,
|
||||
struct pci_bus *bus, u32 devfn, u32 where,
|
||||
u32 * val)
|
||||
{
|
||||
u32 bus_num, slot_num, func_num;
|
||||
|
|
@ -153,7 +153,7 @@ static int read_config_dword(struct pci_config_swap *swap,
|
|||
}
|
||||
|
||||
static int read_config_word(struct pci_config_swap *swap,
|
||||
struct pci_bus *bus, u32 devfn, u32 where,
|
||||
struct pci_bus *bus, u32 devfn, u32 where,
|
||||
u16 * val)
|
||||
{
|
||||
int status;
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
/*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ahennessy@mvista.com
|
||||
* ahennessy@mvista.com
|
||||
*
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
|
||||
*
|
||||
* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
|
||||
*
|
||||
* Define the pci_ops for the Toshiba rbtx4927
|
||||
*
|
||||
* Much of the code is derived from the original DDB5074 port by
|
||||
* Much of the code is derived from the original DDB5074 port by
|
||||
* Geert Uytterhoeven <geert@sonycom.com>
|
||||
*
|
||||
* Copyright 2004 MontaVista Software Inc.
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ struct pci_controller ddb5477_io_controller = {
|
|||
*/
|
||||
|
||||
/*
|
||||
* irq mapping : device -> pci int # -> vrc4377 irq# ,
|
||||
* irq mapping : device -> pci int # -> vrc4377 irq# ,
|
||||
* ddb5477 board manual page 4 and vrc5477 manual page 46
|
||||
*/
|
||||
|
||||
|
|
@ -137,9 +137,9 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|||
unsigned char *slot_irq_map;
|
||||
unsigned char irq;
|
||||
|
||||
/*
|
||||
/*
|
||||
* We ignore the swizzled slot and pin values. The original
|
||||
* pci_fixup_irq() codes largely base irq number on the dev slot
|
||||
* pci_fixup_irq() codes largely base irq number on the dev slot
|
||||
* numbers because except for one case they are unique even
|
||||
* though there are multiple pci buses.
|
||||
*/
|
||||
|
|
@ -160,7 +160,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
|
|||
|
||||
if (mips_machtype == MACH_NEC_ROCKHOPPERII) {
|
||||
/* hack to distinquish overlapping slot 20s, one
|
||||
* on bus 0 (ALI USB on the M1535 on the backplane),
|
||||
* on bus 0 (ALI USB on the M1535 on the backplane),
|
||||
* and one on bus 2 (NEC USB controller on the CPU board)
|
||||
* Make the M1535 USB - ISA IRQ number 9.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ static int __init pcibios_init(void)
|
|||
hose->need_domain_info = need_domain_info;
|
||||
next_busno = bus->subordinate + 1;
|
||||
/* Don't allow 8-bit bus number overflow inside the hose -
|
||||
reserve some space for bridges. */
|
||||
reserve some space for bridges. */
|
||||
if (next_busno > 224) {
|
||||
next_busno = 0;
|
||||
need_domain_info = 1;
|
||||
|
|
@ -260,7 +260,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
|
|||
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
|
||||
pci_read_bridge_bases(bus);
|
||||
pcibios_fixup_device_resources(dev, bus);
|
||||
}
|
||||
}
|
||||
|
||||
for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
|
||||
struct pci_dev *dev = pci_dev_b(ln);
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
*
|
||||
* This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
|
||||
* 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
|
||||
* uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
|
||||
* uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
|
||||
* expected to have a connectivity from the EEPROM to the serial port. This program does
|
||||
* __not__ communicate using the I2C protocol
|
||||
*/
|
||||
|
|
@ -64,14 +64,14 @@ static void send_ack(void)
|
|||
static void send_byte(unsigned char byte)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 7; i >= 0; i--)
|
||||
|
||||
for (i = 7; i >= 0; i--)
|
||||
send_bit((byte >> i) & 0x01);
|
||||
}
|
||||
|
||||
|
||||
static void send_start(void)
|
||||
{
|
||||
sda_hi;
|
||||
sda_hi;
|
||||
delay(TXX);
|
||||
scl_hi;
|
||||
delay(TXX);
|
||||
|
|
@ -114,9 +114,9 @@ static unsigned char recv_byte(void) {
|
|||
int i;
|
||||
unsigned char byte=0;
|
||||
|
||||
for (i=7;i>=0;i--)
|
||||
for (i=7;i>=0;i--)
|
||||
byte |= (recv_bit() << i);
|
||||
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
*/
|
||||
|
||||
/*
|
||||
* Header file for atmel_read_eeprom.c
|
||||
* Header file for atmel_read_eeprom.c
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
|
@ -46,7 +46,7 @@
|
|||
#define DEFAULT_PORT "/dev/ttyS0" /* Port to open */
|
||||
#define TXX 0 /* Dummy loop for spinning */
|
||||
|
||||
#define BLOCK_SEL 0x00
|
||||
#define BLOCK_SEL 0x00
|
||||
#define SLAVE_ADDR 0xa0
|
||||
#define READ_BIT 0x01
|
||||
#define WRITE_BIT 0x00
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ int __init ip22_eisa_init(void)
|
|||
int i, c;
|
||||
char *str;
|
||||
u8 *slot_addr;
|
||||
|
||||
|
||||
if (!(sgimc->systemid & SGIMC_SYSID_EPRESENT)) {
|
||||
printk(KERN_INFO "EISA: bus not present.\n");
|
||||
return 1;
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ void __init sgihpc_init(void)
|
|||
sgint = &sgioc->int3;
|
||||
system_type = "SGI Indy";
|
||||
}
|
||||
|
||||
|
||||
sgi_ioc_reset = (SGIOC_RESET_PPORT | SGIOC_RESET_KBDMOUSE |
|
||||
SGIOC_RESET_EISA | SGIOC_RESET_ISDN |
|
||||
SGIOC_RESET_LC0OFF);
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
/* #define DEBUG_SGINT */
|
||||
|
||||
/* So far nothing hangs here */
|
||||
#undef USE_LIO3_IRQ
|
||||
#undef USE_LIO3_IRQ
|
||||
|
||||
struct sgint_regs *sgint;
|
||||
|
||||
|
|
@ -272,32 +272,32 @@ void indy_buserror_irq(struct pt_regs *regs)
|
|||
irq_exit();
|
||||
}
|
||||
|
||||
static struct irqaction local0_cascade = {
|
||||
static struct irqaction local0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = SA_INTERRUPT,
|
||||
.name = "local0 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction local1_cascade = {
|
||||
static struct irqaction local1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = SA_INTERRUPT,
|
||||
.name = "local1 cascade",
|
||||
};
|
||||
|
||||
static struct irqaction buserr = {
|
||||
static struct irqaction buserr = {
|
||||
.handler = no_action,
|
||||
.flags = SA_INTERRUPT,
|
||||
.name = "Bus Error",
|
||||
};
|
||||
|
||||
static struct irqaction map0_cascade = {
|
||||
static struct irqaction map0_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = SA_INTERRUPT,
|
||||
.name = "mapable0 cascade",
|
||||
};
|
||||
|
||||
#ifdef USE_LIO3_IRQ
|
||||
static struct irqaction map1_cascade = {
|
||||
static struct irqaction map1_cascade = {
|
||||
.handler = no_action,
|
||||
.flags = SA_INTERRUPT,
|
||||
.name = "mapable1 cascade",
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
*ptr |= EEPROM_CSEL; \
|
||||
*ptr |= EEPROM_ECLK; })
|
||||
|
||||
|
||||
|
||||
#define eeprom_cs_off(ptr) ({ \
|
||||
*ptr &= ~EEPROM_ECLK; \
|
||||
*ptr &= ~EEPROM_CSEL; \
|
||||
|
|
@ -50,7 +50,7 @@
|
|||
/*
|
||||
* clock in the nvram command and the register number. For the
|
||||
* national semiconductor nv ram chip the op code is 3 bits and
|
||||
* the address is 6/8 bits.
|
||||
* the address is 6/8 bits.
|
||||
*/
|
||||
static inline void eeprom_cmd(volatile unsigned int *ctrl, unsigned cmd,
|
||||
unsigned reg)
|
||||
|
|
@ -90,7 +90,7 @@ unsigned short ip22_eeprom_read(volatile unsigned int *ctrl, int reg)
|
|||
if (*ctrl & EEPROM_DATI)
|
||||
res |= 1;
|
||||
}
|
||||
|
||||
|
||||
eeprom_cs_off(ctrl);
|
||||
|
||||
return res;
|
||||
|
|
@ -113,7 +113,7 @@ unsigned short ip22_nvram_read(int reg)
|
|||
reg <<= 1;
|
||||
tmp = hpc3c0->bbram[reg++] & 0xff;
|
||||
return (tmp << 8) | (hpc3c0->bbram[reg] & 0xff);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(ip22_nvram_read);
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ static irqreturn_t panel_int(int irq, void *dev_id, struct pt_regs *regs)
|
|||
add_timer(&debounce_timer);
|
||||
}
|
||||
|
||||
/* Power button was pressed
|
||||
/* Power button was pressed
|
||||
* ioc.ps page 22: "The Panel Register is called Power Control by Full
|
||||
* House. Only lowest 2 bits are used. Guiness uses upper four bits
|
||||
* for volume control". This is not true, all bits are pulled high
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@ static __init void indy_time_init(void)
|
|||
unsigned long r4k_ticks[3];
|
||||
unsigned long r4k_tick;
|
||||
|
||||
/*
|
||||
/*
|
||||
* Figure out the r4k offset, the algorithm is very simple and works in
|
||||
* _all_ cases as long as the 8254 counter register itself works ok (as
|
||||
* an interrupt driving timer it does not because of bug, this is why
|
||||
|
|
|
|||
|
|
@ -538,7 +538,7 @@ void __init mem_init(void)
|
|||
for_each_online_node(node) {
|
||||
unsigned slot, numslots;
|
||||
struct page *end, *p;
|
||||
|
||||
|
||||
/*
|
||||
* This will free up the bootmem, ie, slot 0 memory.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static irqreturn_t ip32_rtc_int(int irq, void *dev_id, struct pt_regs *regs)
|
|||
|
||||
reg_c = CMOS_READ(RTC_INTR_FLAGS);
|
||||
if (!(reg_c & RTC_IRQF)) {
|
||||
printk(KERN_WARNING
|
||||
printk(KERN_WARNING
|
||||
"%s: RTC IRQ without RTC_IRQF\n", __FUNCTION__);
|
||||
}
|
||||
/* Wait until interrupt goes away */
|
||||
|
|
|
|||
|
|
@ -17,15 +17,15 @@
|
|||
*/
|
||||
|
||||
/* *********************************************************************
|
||||
*
|
||||
*
|
||||
* Broadcom Common Firmware Environment (CFE)
|
||||
*
|
||||
*
|
||||
* Error codes File: cfe_error.h
|
||||
*
|
||||
*
|
||||
* CFE's global error code list is here.
|
||||
*
|
||||
*
|
||||
* Author: Mitch Lichtenberg
|
||||
*
|
||||
*
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ static void cfe_console_write(struct console *cons, const char *str,
|
|||
last += written;
|
||||
} while (last < count);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
static int cfe_console_setup(struct console *cons, char *str)
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@ void __init prom_init(void)
|
|||
while (1) ;
|
||||
}
|
||||
cfe_init(cfe_handle, cfe_ept);
|
||||
/*
|
||||
/*
|
||||
* Get the handle for (at least) prom_putchar, possibly for
|
||||
* boot console
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ void __init prom_prepare_cpus(unsigned int max_cpus)
|
|||
void prom_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
int retval;
|
||||
|
||||
|
||||
retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
|
||||
__KSTK_TOS(idle),
|
||||
(unsigned long)idle->thread_info, 0);
|
||||
|
|
|
|||
|
|
@ -10,13 +10,13 @@
|
|||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
/*
|
||||
* The Bus Watcher monitors internal bus transactions and maintains
|
||||
* counts of transactions with error status, logging details and
|
||||
* causing one of several interrupts. This driver provides a handler
|
||||
|
|
@ -155,7 +155,7 @@ static int bw_read_proc(char *page, char **start, off_t off,
|
|||
static void create_proc_decoder(struct bw_stats_struct *stats)
|
||||
{
|
||||
struct proc_dir_entry *ent;
|
||||
|
||||
|
||||
ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
|
||||
bw_read_proc, stats);
|
||||
if (!ent) {
|
||||
|
|
|
|||
|
|
@ -377,7 +377,7 @@ void __init arch_init_irq(void)
|
|||
|
||||
/*
|
||||
* Note that the timer interrupts are also mapped, but this is
|
||||
* done in sb1250_time_init(). Also, the profiling driver
|
||||
* done in sb1250_time_init(). Also, the profiling driver
|
||||
* does its own management of IP7.
|
||||
*/
|
||||
|
||||
|
|
@ -392,7 +392,7 @@ void __init arch_init_irq(void)
|
|||
if (kgdb_flag) {
|
||||
kgdb_irq = K_INT_UART_0 + kgdb_port;
|
||||
|
||||
#ifdef CONFIG_SIBYTE_SB1250_DUART
|
||||
#ifdef CONFIG_SIBYTE_SB1250_DUART
|
||||
sb1250_duart_present[kgdb_port] = 0;
|
||||
#endif
|
||||
/* Setup uart 1 settings, mapper */
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ static int m41t81_write(uint8_t addr, int b)
|
|||
/* Clear error bit by writing a 1 */
|
||||
bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* read the same byte again to make sure it is written */
|
||||
bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
|
||||
|
|
@ -136,7 +136,7 @@ static int m41t81_write(uint8_t addr, int b)
|
|||
|
||||
while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
|
||||
;
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -148,13 +148,13 @@ int m41t81_set_time(unsigned long t)
|
|||
|
||||
/*
|
||||
* Note the write order matters as it ensures the correctness.
|
||||
* When we write sec, 10th sec is clear. It is reasonable to
|
||||
* When we write sec, 10th sec is clear. It is reasonable to
|
||||
* believe we should finish writing min within a second.
|
||||
*/
|
||||
|
||||
tm.tm_sec = BIN2BCD(tm.tm_sec);
|
||||
m41t81_write(M41T81REG_SC, tm.tm_sec);
|
||||
|
||||
|
||||
tm.tm_min = BIN2BCD(tm.tm_min);
|
||||
m41t81_write(M41T81REG_MN, tm.tm_min);
|
||||
|
||||
|
|
@ -187,7 +187,7 @@ unsigned long m41t81_get_time(void)
|
|||
{
|
||||
unsigned int year, mon, day, hour, min, sec;
|
||||
|
||||
/*
|
||||
/*
|
||||
* min is valid if two reads of sec are the same.
|
||||
*/
|
||||
for (;;) {
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ static int __init swarm_setup(void)
|
|||
rtc_get_time = xicor_get_time;
|
||||
rtc_set_time = xicor_set_time;
|
||||
}
|
||||
|
||||
|
||||
if (m41t81_probe()) {
|
||||
printk("swarm setup: M41T81 RTC detected.\n");
|
||||
rtc_get_time = m41t81_get_time;
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ static unsigned int ls1bit8(unsigned int x)
|
|||
|
||||
/*
|
||||
* hwint 1 deals with EISA and SCSI interrupts,
|
||||
*
|
||||
*
|
||||
* The EISA_INT bit in CSITPEND is high active, all others are low active.
|
||||
*/
|
||||
void pciasic_hwint1(struct pt_regs *regs)
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ static struct resource sni_mem_resource = {
|
|||
* The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
|
||||
* for other purposes. Be paranoid and allocate all of the before the PCI
|
||||
* code gets a chance to to map anything else there ...
|
||||
*
|
||||
*
|
||||
* This leaves the following areas available:
|
||||
*
|
||||
* 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
|
||||
|
|
|
|||
|
|
@ -42,13 +42,13 @@
|
|||
CLI
|
||||
.set at
|
||||
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t0, CP0_CAUSE
|
||||
mfc0 t1, CP0_STATUS
|
||||
and t0, t1
|
||||
|
||||
|
||||
andi t1, t0, STATUSF_IP7 /* cpu timer */
|
||||
bnez t1, ll_ip7
|
||||
|
||||
|
||||
/* IP6..IP3 multiplexed -- do not use */
|
||||
|
||||
andi t1, t0, STATUSF_IP2 /* tx4927 pic */
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ dump_cp0(char *key)
|
|||
print_cp0(key, 16, "CONFIG ", read_c0_config());
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
void print_pic(char *key, u32 reg, char *name)
|
||||
{
|
||||
printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
obj-y += toshiba_rbtx4927_prom.o
|
||||
obj-y += toshiba_rbtx4927_setup.o
|
||||
obj-y += toshiba_rbtx4927_irq.o
|
||||
obj-y += toshiba_rbtx4927_prom.o
|
||||
obj-y += toshiba_rbtx4927_setup.o
|
||||
obj-y += toshiba_rbtx4927_irq.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
|
||||
/*
|
||||
IRQ Device
|
||||
IRQ Device
|
||||
00 RBTX4927-ISA/00
|
||||
01 RBTX4927-ISA/01 PS2/Keyboard
|
||||
02 RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
|
||||
|
|
@ -52,15 +52,15 @@ IRQ Device
|
|||
16 TX4927-CP0/00 Software 0
|
||||
17 TX4927-CP0/01 Software 1
|
||||
18 TX4927-CP0/02 Cascade TX4927-CP0
|
||||
19 TX4927-CP0/03 Multiplexed -- do not use
|
||||
20 TX4927-CP0/04 Multiplexed -- do not use
|
||||
21 TX4927-CP0/05 Multiplexed -- do not use
|
||||
22 TX4927-CP0/06 Multiplexed -- do not use
|
||||
19 TX4927-CP0/03 Multiplexed -- do not use
|
||||
20 TX4927-CP0/04 Multiplexed -- do not use
|
||||
21 TX4927-CP0/05 Multiplexed -- do not use
|
||||
22 TX4927-CP0/06 Multiplexed -- do not use
|
||||
23 TX4927-CP0/07 CPU TIMER
|
||||
|
||||
24 TX4927-PIC/00
|
||||
25 TX4927-PIC/01
|
||||
26 TX4927-PIC/02
|
||||
26 TX4927-PIC/02
|
||||
27 TX4927-PIC/03 Cascade RBTX4927-IOC
|
||||
28 TX4927-PIC/04
|
||||
29 TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
|
||||
|
|
@ -80,7 +80,7 @@ IRQ Device
|
|||
43 TX4927-PIC/19
|
||||
44 TX4927-PIC/20
|
||||
45 TX4927-PIC/21
|
||||
46 TX4927-PIC/22 TX4927 PCI PCI-ERR
|
||||
46 TX4927-PIC/22 TX4927 PCI PCI-ERR
|
||||
47 TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
|
||||
48 TX4927-PIC/24
|
||||
49 TX4927-PIC/25
|
||||
|
|
@ -100,7 +100,7 @@ IRQ Device
|
|||
62 RBTX4927-IOC/06
|
||||
63 RBTX4927-IOC/07
|
||||
|
||||
NOTES:
|
||||
NOTES:
|
||||
SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
|
||||
SouthBridge/ISA/pin=0 no pci irq used by this device
|
||||
SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
|
||||
|
|
@ -175,19 +175,19 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
|
|||
static const u32 toshiba_rbtx4927_irq_debug_flag =
|
||||
(TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
|
||||
TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
|
||||
// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
|
||||
// | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
|
||||
);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -395,7 +395,7 @@ static int __init tx4927_pcibios_init(void)
|
|||
/* enable secondary ide */
|
||||
v08_43 |= 0x80;
|
||||
|
||||
/*
|
||||
/*
|
||||
* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
|
||||
*
|
||||
* This line of code is intended to provide the user with a work
|
||||
|
|
|
|||
|
|
@ -476,7 +476,7 @@ static inline int vrc4173_icu_init(int cascade_irq)
|
|||
|
||||
if (cascade_irq < GIU_IRQ(0) || cascade_irq > GIU_IRQ(15))
|
||||
return -EINVAL;
|
||||
|
||||
|
||||
vrc4173_outw(0, VRC4173_MSYSINT1REG);
|
||||
|
||||
vr41xx_set_irq_trigger(GIU_IRQ_TO_PIN(cascade_irq), TRIGGER_LEVEL, SIGNAL_THROUGH);
|
||||
|
|
|
|||
|
|
@ -7,10 +7,10 @@
|
|||
*/
|
||||
#ifndef _ASM_ASMMACRO_H
|
||||
#define _ASM_ASMMACRO_H
|
||||
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <asm/hazards.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
#include <asm/asmmacro-32.h>
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,13 +20,13 @@
|
|||
#define SZLONG_MASK 31UL
|
||||
#define __LL "ll "
|
||||
#define __SC "sc "
|
||||
#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
|
||||
#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
|
||||
#elif (_MIPS_SZLONG == 64)
|
||||
#define SZLONG_LOG 6
|
||||
#define SZLONG_MASK 63UL
|
||||
#define __LL "lld "
|
||||
#define __SC "scd "
|
||||
#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
|
||||
#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
|
||||
#endif
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
|
|||
* All PCI irq but INTC are active low.
|
||||
*/
|
||||
|
||||
/*
|
||||
/*
|
||||
* irq number block assignment
|
||||
*/
|
||||
|
||||
|
|
@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
|
|||
#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
|
||||
#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
|
||||
#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
|
||||
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
|
||||
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
|
||||
#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
|
||||
#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
|
||||
#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
|
||||
|
|
@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
|
|||
/*
|
||||
* i2859 irq assignment
|
||||
*/
|
||||
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
|
||||
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
|
||||
#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
|
||||
#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
|
||||
#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#define _ASM_FPREGDEF_H
|
||||
|
||||
#include <asm/sgidefs.h>
|
||||
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI32
|
||||
|
||||
/*
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
#define fcr31 $31 /* FPU status register */
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
|
||||
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
|
||||
#define fv0 $f0 /* return value */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue