drm/nouveau/clk/gk20a: share reusable structures/functions
Make functions/structures that the GM20B driver will reuse public. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -22,8 +22,8 @@
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* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
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*
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*/
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#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
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#include "priv.h"
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#include "gk20a.h"
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#include <core/tegra.h>
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#include <subdev/timer.h>
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@ -33,9 +33,6 @@
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#define MASK(w) ((1 << w) - 1)
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#define SYS_GPCPLL_CFG_BASE 0x00137000
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#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800
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#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)
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#define GPCPLL_CFG_ENABLE BIT(0)
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#define GPCPLL_CFG_IDDQ BIT(1)
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@ -57,6 +54,7 @@
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#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)
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#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16
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#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800
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#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0
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#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8
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@ -76,7 +74,7 @@
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#define GPC2CLK_OUT_VCODIV1 0
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#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \
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GPC2CLK_OUT_VCODIV_SHIFT)
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#define GPC2CLK_OUT_BYPDIV_WIDTH 6
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#define GPC2CLK_OUT_BYPDIV_WIDTH 6
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#define GPC2CLK_OUT_BYPDIV_SHIFT 0
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#define GPC2CLK_OUT_BYPDIV31 0x3c
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#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \
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@ -98,14 +96,6 @@ static const u8 _pl_to_div[] = {
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/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32,
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};
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/* All frequencies in Khz */
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struct gk20a_clk_pllg_params {
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u32 min_vco, max_vco;
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u32 min_u, max_u;
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u32 min_m, max_m;
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u32 min_n, max_n;
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u32 min_pl, max_pl;
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};
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static u32 pl_to_div(u32 pl)
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{
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if (pl >= ARRAY_SIZE(_pl_to_div))
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@ -134,22 +124,6 @@ static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
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.min_pl = 1, .max_pl = 32,
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};
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struct gk20a_pll {
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u32 m;
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u32 n;
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u32 pl;
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};
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struct gk20a_clk {
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struct nvkm_clk base;
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const struct gk20a_clk_pllg_params *params;
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struct gk20a_pll pll;
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u32 parent_rate;
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u32 (*div_to_pl)(u32);
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u32 (*pl_to_div)(u32);
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};
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static void
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gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
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{
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@ -472,8 +446,6 @@ gk20a_pllg_program_mnp(struct gk20a_clk *clk)
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return err;
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}
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#define GK20A_CLK_GPC_MDIV 1000
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static struct nvkm_pstate
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gk20a_pstates[] = {
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{
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@ -568,7 +540,7 @@ gk20a_pstates[] = {
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},
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};
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static int
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int
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gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
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@ -587,7 +559,7 @@ gk20a_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
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}
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}
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static int
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int
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gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
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@ -596,7 +568,7 @@ gk20a_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
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GK20A_CLK_GPC_MDIV);
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}
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static int
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int
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gk20a_clk_prog(struct nvkm_clk *base)
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{
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struct gk20a_clk *clk = gk20a_clk(base);
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@ -604,12 +576,12 @@ gk20a_clk_prog(struct nvkm_clk *base)
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return gk20a_pllg_program_mnp(clk);
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}
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static void
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void
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gk20a_clk_tidy(struct nvkm_clk *base)
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{
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}
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static void
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void
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gk20a_clk_fini(struct nvkm_clk *base)
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{
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struct nvkm_device *device = base->subdev.device;
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65
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
Normal file
65
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.h
Normal file
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@ -0,0 +1,65 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NVKM_CLK_GK20A_H__
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#define __NVKM_CLK_GK20A_H__
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#define GK20A_CLK_GPC_MDIV 1000
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#define SYS_GPCPLL_CFG_BASE 0x00137000
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/* All frequencies in Khz */
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struct gk20a_clk_pllg_params {
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u32 min_vco, max_vco;
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u32 min_u, max_u;
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u32 min_m, max_m;
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u32 min_n, max_n;
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u32 min_pl, max_pl;
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};
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struct gk20a_pll {
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u32 m;
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u32 n;
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u32 pl;
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};
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struct gk20a_clk {
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struct nvkm_clk base;
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const struct gk20a_clk_pllg_params *params;
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struct gk20a_pll pll;
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u32 parent_rate;
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u32 (*div_to_pl)(u32);
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u32 (*pl_to_div)(u32);
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};
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#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
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int _gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *,
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const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
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void gk20a_clk_fini(struct nvkm_clk *);
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int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
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int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
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int gk20a_clk_prog(struct nvkm_clk *);
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void gk20a_clk_tidy(struct nvkm_clk *);
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#endif
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