powerpc: Convert flush_icache_range & friends to C
[ Upstream commit5.4-rM2-2.2.x-imx-squashed23eb7f560a] Similar to commit22e9c88d48("powerpc/64: reuse PPC32 static inline flush_dcache_range()") this patch converts the following ASM symbols to C: flush_icache_range() __flush_dcache_icache() __flush_dcache_icache_phys() This was done as we discovered a long-standing bug where the length of the range was truncated due to using a 32 bit shift instead of a 64 bit one. By converting these functions to C, it becomes easier to maintain. flush_dcache_icache_phys() retains a critical assembler section as we must ensure there are no memory accesses while the data MMU is disabled (authored by Christophe Leroy). Since this has no external callers, it has also been made static, allowing the compiler to inline it within flush_dcache_icache_page(). Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> [mpe: Minor fixups, don't export __flush_dcache_icache()] Link: https://lore.kernel.org/r/20191104023305.9581-5-alastair@au1.ibm.com Signed-off-by: Sasha Levin <sashal@kernel.org>
Alastair D'Silva
Greg Kroah-Hartman
parent
ec21f6d52b
commit
42dac16dc4
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@ -96,22 +96,7 @@ static inline u32 l1_icache_bytes(void)
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}
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#endif
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#endif /* ! __ASSEMBLY__ */
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#if defined(__ASSEMBLY__)
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/*
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* For a snooping icache, we still need a dummy icbi to purge all the
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* prefetched instructions from the ifetch buffers. We also need a sync
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* before the icbi to order the the actual stores to memory that might
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* have modified instructions with the icbi.
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*/
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#define PURGE_PREFETCHED_INS \
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sync; \
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icbi 0,r3; \
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sync; \
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isync
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#else
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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#ifdef CONFIG_PPC_BOOK3S_32
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@ -145,6 +130,17 @@ static inline void dcbst(void *addr)
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{
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__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
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}
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static inline void icbi(void *addr)
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{
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asm volatile ("icbi 0, %0" : : "r"(addr) : "memory");
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}
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static inline void iccci(void *addr)
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{
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asm volatile ("iccci 0, %0" : : "r"(addr) : "memory");
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHE_H */
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@ -42,24 +42,20 @@ extern void flush_dcache_page(struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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extern void flush_icache_range(unsigned long, unsigned long);
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void flush_icache_range(unsigned long start, unsigned long stop);
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extern void flush_icache_user_range(struct vm_area_struct *vma,
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struct page *page, unsigned long addr,
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int len);
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extern void __flush_dcache_icache(void *page_va);
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extern void flush_dcache_icache_page(struct page *page);
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#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
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extern void __flush_dcache_icache_phys(unsigned long physaddr);
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#else
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static inline void __flush_dcache_icache_phys(unsigned long physaddr)
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{
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BUG();
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}
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#endif
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void __flush_dcache_icache(void *page);
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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/**
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* flush_dcache_range(): Write any modified data cache blocks out to memory and
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* invalidate them. Does not invalidate the corresponding instruction cache
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* blocks.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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static inline void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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@ -316,126 +316,6 @@ _GLOBAL(flush_instruction_cache)
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EXPORT_SYMBOL(flush_instruction_cache)
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#endif /* CONFIG_PPC_8xx */
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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* This is a no-op on the 601.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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#if defined(CONFIG_PPC_BOOK3S_601) || defined(CONFIG_E200)
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PURGE_PREFETCHED_INS
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blr /* for 601 and e200, do nothing */
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#else
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rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
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subf r4,r3,r4
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addi r4,r4,L1_CACHE_BYTES - 1
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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#ifndef CONFIG_44x
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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#else
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/* Flash invalidate on 44x because we are passed kmapped addresses and
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this doesn't work for userspace pages due to the virtually tagged
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icache. Sigh. */
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iccci 0, r0
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#endif
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sync /* additional sync needed on g4 */
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isync
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blr
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#endif
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_ASM_NOKPROBE_SYMBOL(flush_icache_range)
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EXPORT_SYMBOL(flush_icache_range)
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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* This is a no-op on the 601 and e200 which have a unified cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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#if defined(CONFIG_PPC_BOOK3S_601) || defined(CONFIG_E200)
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PURGE_PREFETCHED_INS
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blr
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#else
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,L1_CACHE_BYTES
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bdnz 0b
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sync
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#ifdef CONFIG_44x
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/* We don't flush the icache on 44x. Those have a virtual icache
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* and we don't have access to the virtual address here (it's
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* not the page vaddr but where it's mapped in user space). The
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* flushing of the icache on these is handled elsewhere, when
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* a change in the address space occurs, before returning to
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* user space
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*/
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BEGIN_MMU_FTR_SECTION
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blr
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_44x)
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#endif /* CONFIG_44x */
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 1b
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sync
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isync
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blr
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#endif
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#ifndef CONFIG_BOOKE
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/*
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* Flush a particular page from the data cache to RAM, identified
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* by its physical address. We turn off the MMU so we can just use
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* the physical address (this may be a highmem page without a kernel
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* mapping).
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*
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* void __flush_dcache_icache_phys(unsigned long physaddr)
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*/
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_GLOBAL(__flush_dcache_icache_phys)
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#if defined(CONFIG_PPC_BOOK3S_601) || defined(CONFIG_E200)
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PURGE_PREFETCHED_INS
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blr /* for 601 and e200, do nothing */
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#else
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mfmsr r10
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rlwinm r0,r10,0,28,26 /* clear DR */
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mtmsr r0
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isync
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rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
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li r4,PAGE_SIZE/L1_CACHE_BYTES /* Number of lines in a page */
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mtctr r4
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mr r6,r3
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0: dcbst 0,r3 /* Write line to ram */
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addi r3,r3,L1_CACHE_BYTES
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bdnz 0b
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sync
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mtctr r4
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1: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 1b
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sync
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mtmsr r10 /* restore DR */
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isync
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blr
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#endif
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#endif /* CONFIG_BOOKE */
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/*
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* Copy a whole page. We use the dcbz instruction on the destination
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* to reduce memory traffic (it eliminates the unnecessary reads of
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@ -49,108 +49,6 @@ _GLOBAL(call_do_irq)
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mtlr r0
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blr
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.section ".toc","aw"
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PPC64_CACHES:
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.tc ppc64_caches[TC],ppc64_caches
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.section ".text"
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*
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* flush all bytes from start through stop-1 inclusive
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*/
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_GLOBAL_TOC(flush_icache_range)
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BEGIN_FTR_SECTION
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PURGE_PREFETCHED_INS
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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* and in some cases i-cache and d-cache line sizes differ from
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* each other.
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*/
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ld r10,PPC64_CACHES@toc(r2)
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lwz r7,DCACHEL1BLOCKSIZE(r10)/* Get cache block size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
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srd. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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add r6,r6,r7
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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lwz r7,ICACHEL1BLOCKSIZE(r10) /* Get Icache block size */
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addi r5,r7,-1
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andc r6,r3,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
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srd. r8,r8,r9 /* compute line count */
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beqlr /* nothing to do? */
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mtctr r8
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2: icbi 0,r6
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add r6,r6,r7
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bdnz 2b
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isync
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blr
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_ASM_NOKPROBE_SYMBOL(flush_icache_range)
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EXPORT_SYMBOL(flush_icache_range)
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/*
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* Flush a particular page from the data cache to RAM.
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* Note: this is necessary because the instruction cache does *not*
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* snoop from the data cache.
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*
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* void __flush_dcache_icache(void *page)
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*/
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_GLOBAL(__flush_dcache_icache)
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/*
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* Flush the data cache to memory
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*
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* Different systems have different cache line sizes
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*/
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BEGIN_FTR_SECTION
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PURGE_PREFETCHED_INS
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blr
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END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
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/* Flush the dcache */
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ld r7,PPC64_CACHES@toc(r2)
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clrrdi r3,r3,PAGE_SHIFT /* Page align */
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lwz r4,DCACHEL1BLOCKSPERPAGE(r7) /* Get # dcache blocks per page */
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lwz r5,DCACHEL1BLOCKSIZE(r7) /* Get dcache block size */
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mr r6,r3
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mtctr r4
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0: dcbst 0,r6
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add r6,r6,r5
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bdnz 0b
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sync
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/* Now invalidate the icache */
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lwz r4,ICACHEL1BLOCKSPERPAGE(r7) /* Get # icache blocks per page */
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lwz r5,ICACHEL1BLOCKSIZE(r7) /* Get icache block size */
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mtctr r4
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1: icbi 0,r3
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add r3,r3,r5
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bdnz 1b
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isync
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blr
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_GLOBAL(__bswapdi2)
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EXPORT_SYMBOL(__bswapdi2)
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srdi r8,r3,32
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@ -348,6 +348,120 @@ void free_initmem(void)
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free_initmem_default(POISON_FREE_INITMEM);
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}
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/**
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* flush_coherent_icache() - if a CPU has a coherent icache, flush it
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* @addr: The base address to use (can be any valid address, the whole cache will be flushed)
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* Return true if the cache was flushed, false otherwise
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*/
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static inline bool flush_coherent_icache(unsigned long addr)
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{
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/*
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* For a snooping icache, we still need a dummy icbi to purge all the
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* prefetched instructions from the ifetch buffers. We also need a sync
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* before the icbi to order the the actual stores to memory that might
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* have modified instructions with the icbi.
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*/
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
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mb(); /* sync */
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icbi((void *)addr);
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mb(); /* sync */
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isync();
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return true;
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}
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return false;
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}
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/**
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* invalidate_icache_range() - Flush the icache by issuing icbi across an address range
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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static void invalidate_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long shift = l1_icache_shift();
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unsigned long bytes = l1_icache_bytes();
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char *addr = (char *)(start & ~(bytes - 1));
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unsigned long size = stop - (unsigned long)addr + (bytes - 1);
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unsigned long i;
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for (i = 0; i < size >> shift; i++, addr += bytes)
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icbi(addr);
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mb(); /* sync */
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isync();
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}
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/**
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* flush_icache_range: Write any modified data cache blocks out to memory
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* and invalidate the corresponding blocks in the instruction cache
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*
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* Generic code will call this after writing memory, before executing from it.
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*
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* @start: the start address
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* @stop: the stop address (exclusive)
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*/
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void flush_icache_range(unsigned long start, unsigned long stop)
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{
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if (flush_coherent_icache(start))
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return;
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clean_dcache_range(start, stop);
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if (IS_ENABLED(CONFIG_44x)) {
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/*
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* Flash invalidate on 44x because we are passed kmapped
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* addresses and this doesn't work for userspace pages due to
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* the virtually tagged icache.
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*/
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iccci((void *)start);
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mb(); /* sync */
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isync();
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} else
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invalidate_icache_range(start, stop);
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}
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EXPORT_SYMBOL(flush_icache_range);
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#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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/**
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* flush_dcache_icache_phys() - Flush a page by it's physical address
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* @physaddr: the physical address of the page
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*/
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static void flush_dcache_icache_phys(unsigned long physaddr)
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{
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unsigned long bytes = l1_dcache_bytes();
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unsigned long nb = PAGE_SIZE / bytes;
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unsigned long addr = physaddr & PAGE_MASK;
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unsigned long msr, msr0;
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unsigned long loop1 = addr, loop2 = addr;
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msr0 = mfmsr();
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msr = msr0 & ~MSR_DR;
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/*
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* This must remain as ASM to prevent potential memory accesses
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* while the data MMU is disabled
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*/
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asm volatile(
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" mtctr %2;\n"
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" mtmsr %3;\n"
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" isync;\n"
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"0: dcbst 0, %0;\n"
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" addi %0, %0, %4;\n"
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" bdnz 0b;\n"
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" sync;\n"
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" mtctr %2;\n"
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"1: icbi 0, %1;\n"
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" addi %1, %1, %4;\n"
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" bdnz 1b;\n"
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" sync;\n"
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" mtmsr %5;\n"
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" isync;\n"
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: "+&r" (loop1), "+&r" (loop2)
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: "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
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: "ctr", "memory");
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}
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#endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
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/*
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* This is called when a page has been modified by the kernel.
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* It just marks the page as not i-cache clean. We do the i-cache
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@ -380,12 +494,46 @@ void flush_dcache_icache_page(struct page *page)
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__flush_dcache_icache(start);
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kunmap_atomic(start);
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} else {
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__flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
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||||
unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
|
||||
|
||||
if (flush_coherent_icache(addr))
|
||||
return;
|
||||
flush_dcache_icache_phys(addr);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
EXPORT_SYMBOL(flush_dcache_icache_page);
|
||||
|
||||
/**
|
||||
* __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
|
||||
* Note: this is necessary because the instruction cache does *not*
|
||||
* snoop from the data cache.
|
||||
*
|
||||
* @page: the address of the page to flush
|
||||
*/
|
||||
void __flush_dcache_icache(void *p)
|
||||
{
|
||||
unsigned long addr = (unsigned long)p;
|
||||
|
||||
if (flush_coherent_icache(addr))
|
||||
return;
|
||||
|
||||
clean_dcache_range(addr, addr + PAGE_SIZE);
|
||||
|
||||
/*
|
||||
* We don't flush the icache on 44x. Those have a virtual icache and we
|
||||
* don't have access to the virtual address here (it's not the page
|
||||
* vaddr but where it's mapped in user space). The flushing of the
|
||||
* icache on these is handled elsewhere, when a change in the address
|
||||
* space occurs, before returning to user space.
|
||||
*/
|
||||
|
||||
if (cpu_has_feature(MMU_FTR_TYPE_44x))
|
||||
return;
|
||||
|
||||
invalidate_icache_range(addr, addr + PAGE_SIZE);
|
||||
}
|
||||
|
||||
void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
|
||||
{
|
||||
clear_page(page);
|
||||
|
|
|
|||
Loading…
Reference in New Issue