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clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support 

The new BCM2711 supports an additional clock for the emmc2 block.
So add a new compatible and register this clock only for BCM2711.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
alistair/sunxi64-5.4-dsi
Stefan Wahren 2019-08-18 18:23:43 +02:00 committed by Stephen Boyd
parent ee0a5a9013
commit 42de9ad400
1 changed files with 19 additions and 1 deletions
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20
drivers/clk/bcm/clk-bcm2835.c
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@ -114,6 +114,8 @@
#define CM_AVEODIV 0x1bc
#define CM_EMMCCTL 0x1c0
#define CM_EMMCDIV 0x1c4
#define CM_EMMC2CTL 0x1d0
#define CM_EMMC2DIV 0x1d4
/* General bits for the CM_*CTL regs */
# define CM_ENABLE BIT(4)
@ -290,7 +292,8 @@
#define BCM2835_MAX_FB_RATE 1750000000u
#define SOC_BCM2835 BIT(0)
#define SOC_ALL (SOC_BCM2835)
#define SOC_BCM2711 BIT(1)
#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
/*
* Names of clocks used within the driver that need to be replaced
@ -2003,6 +2006,16 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.frac_bits = 8,
.tcnt_mux = 39),
/* EMMC2 clock (only available for BCM2711) */
[BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
SOC_BCM2711,
.name = "emmc2",
.ctl_reg = CM_EMMC2CTL,
.div_reg = CM_EMMC2DIV,
.int_bits = 4,
.frac_bits = 8,
.tcnt_mux = 42),
/* General purpose (GPIO) clocks */
[BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
SOC_ALL,
@ -2238,8 +2251,13 @@ static const struct cprman_plat_data cprman_bcm2835_plat_data = {
.soc = SOC_BCM2835,
};
static const struct cprman_plat_data cprman_bcm2711_plat_data = {
.soc = SOC_BCM2711,
};
static const struct of_device_id bcm2835_clk_of_match[] = {
{ .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
{ .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
{}
};
MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);