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drm fixes for 5.8-rc5 

amdgpu:
 - Fix a suspend/resume issue with PSP
 - Backlight fix for Renoir
 - Fix for gpu recovery debugging
 
 radeon:
 - Fix a double free in error path
 
 i915:
 - fbc fencing fix
 - debugfs panic fix
 - gem vma constuction fix
 - gem pin under vm->nutex fix
 
 nouveau:
 - SVM fixes
 - display fixes
 
 meson:
 - OSD burst length fixes
 
 hibmc:
 - runtime warning fix
 
 mediatek:
 - cmdq, mmsys fixes
 - visibility check fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJfB7/cAAoJEAx081l5xIa+//gP/jETm7J10bQyUxGxl9tV1E0/
 ymI+zhhdZAv6bXBjnxS7DZc7THai7khLRBeeBD1SuW2c9iGT/tinbea6VicXATEY
 LoRD6lWf6To0fgvAV0GzHIzsG8cap/CJsBu43ir0+cBdw6xpqWN78HabCi+YGwTC
 Dvtj3BA8b3E1VoGASeArq8KxjUJps1RHneq2pbr2vYi3J+FO6lnGtPei9vbnC8/n
 01UtZ9jXQZEJ1zzuqL8KFBlLwJArDBx2G8BqBFCNRznTNUSM7L9NKwsv0lg5X77z
 XSLrhPijbP8BE6B9NrwJxzj2+LqPJez8AGlpyWkTuiPF18UTnIlJ5NXVfw4Ldxlj
 1LgZSKO2SkP+4I41JgTLzBbF1CLJX8GmPM11y6j/lw33YzWU7Sh6WTSng2U88mS0
 NIJ3ARqxrzsfeaWvrLxnNKZwK7qUdC1hu5QV7VsKiOd28pbCgTMjbCx9KEYA10nQ
 rMvdwAK0IvgTUgfhq4+fMZdGm/YFb2odUTP24iOvx/caolMuNUBhwKu2NZP09s4s
 mvJCSpTVLlZHhG13PsbTMYKTRR6T16lDoRMxzklU3XZK6K41+LKdMSH0icCQ5XcO
 kVdAF+BDFwnC4dqqk5N0SG3rwpLd0QI/E1pSonnlpfd98EZXaaFtKEawbLpuVWEW
 mcg+fE5X3711l2vK6/7x
 =K+cQ
 -----END PGP SIGNATURE-----

Merge tag 'drm-fixes-2020-07-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "I've been off most of the week, but some fixes have piled up. Seems a
  bit busier than last week, but they are pretty spread out across a
  bunch of drivers, none of them seem that big or worried me too much.

  amdgpu:
   - Fix a suspend/resume issue with PSP
   - Backlight fix for Renoir
   - Fix for gpu recovery debugging

  radeon:
   - Fix a double free in error path

  i915:
   - fbc fencing fix
   - debugfs panic fix
   - gem vma constuction fix
   - gem pin under vm->nutex fix

  nouveau:
   - SVM fixes
   - display fixes

  meson:
   - OSD burst length fixes

  hibmc:
   - runtime warning fix

  mediatek:
   - cmdq, mmsys fixes
   - visibility check fixes"

* tag 'drm-fixes-2020-07-10' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amdgpu: don't do soft recovery if gpu_recovery=0
  drm/radeon: fix double free
  drm/amd/display: add dmcub check on RENOIR
  drm/amdgpu: add TMR destory function for psp
  drm/amdgpu: asd function needs to be unloaded in suspend phase
  drm/hisilicon/hibmc: Move drm_fbdev_generic_setup() down to avoid the splat
  drm/nouveau/nouveau: fix page fault on device private memory
  drm/nouveau/svm: fix migrate page regression
  drm/nouveau/i2c/g94-: increase NV_PMGR_DP_AUXCTL_TRANSACTREQ timeout
  drm/nouveau/kms/nv50-: bail from nv50_audio_disable() early if audio not enabled
  drm/i915/gt: Pin the rings before marking active
  drm/i915: Also drop vm.ref along error paths for vma construction
  drm/i915: Drop vm.ref for duplicate vma on construction
  drm/i915/fbc: Fix fence_y_offset handling
  drm/i915: Skip stale object handle for debugfs per-file-stats
  drm/mediatek: mtk_hdmi: Remove debug messages for function calls
  drm/mediatek: mtk_mt8173_hdmi_phy: Remove unnused const variables
  drm/mediatek: Delete not used of_device_get_match_data
  drm/mediatek: Remove unnecessary conversion to bool
  drm/meson: viu: fix setting the OSD burst length in VIU_OSD1_FIFO_CTRL_STAT
  ...
alistair/sunxi64-5.8
Linus Torvalds 2020-07-09 18:20:19 -07:00
parent d4e6045326 38794a5465
commit 42f82040ee
26 changed files with 145 additions and 155 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
View File

@ -37,7 +37,8 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
memset(&ti, 0, sizeof(struct amdgpu_task_info));
if (amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
if (amdgpu_gpu_recovery &&
amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
DRM_ERROR("ring %s timeout, but soft recovered\n",
s_job->sched->name);
return;

63
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -372,6 +372,52 @@ static int psp_tmr_load(struct psp_context *psp)
return ret;
}
static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
struct psp_gfx_cmd_resp *cmd)
{
if (amdgpu_sriov_vf(psp->adev))
cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
else
cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
}
static int psp_tmr_unload(struct psp_context *psp)
{
int ret;
struct psp_gfx_cmd_resp *cmd;
cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
if (!cmd)
return -ENOMEM;
psp_prep_tmr_unload_cmd_buf(psp, cmd);
DRM_INFO("free PSP TMR buffer\n");
ret = psp_cmd_submit_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
kfree(cmd);
return ret;
}
static int psp_tmr_terminate(struct psp_context *psp)
{
int ret;
void *tmr_buf;
void **pptr;
ret = psp_tmr_unload(psp);
if (ret)
return ret;
/* free TMR memory buffer */
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
return 0;
}
static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
uint64_t asd_mc, uint32_t size)
{
@ -1779,8 +1825,6 @@ static int psp_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
void *tmr_buf;
void **pptr;
if (psp->adev->psp.ta_fw) {
psp_ras_terminate(psp);
@ -1790,10 +1834,9 @@ static int psp_hw_fini(void *handle)
psp_asd_unload(psp);
psp_tmr_terminate(psp);
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
amdgpu_bo_free_kernel(&psp->fw_pri_bo,
&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
amdgpu_bo_free_kernel(&psp->fence_buf_bo,
@ -1840,6 +1883,18 @@ static int psp_suspend(void *handle)
}
}
ret = psp_asd_unload(psp);
if (ret) {
DRM_ERROR("Failed to unload asd\n");
return ret;
}
ret = psp_tmr_terminate(psp);
if (ret) {
DRM_ERROR("Falied to terminate tmr\n");
return ret;
}
ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
if (ret) {
DRM_ERROR("PSP ring stop failed\n");

2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -1358,7 +1358,7 @@ static int dm_late_init(void *handle)
struct dmcu *dmcu = NULL;
bool ret;
if (!adev->dm.fw_dmcu)
if (!adev->dm.fw_dmcu && !adev->dm.dmub_fw)
return detect_mst_link_for_all_connectors(adev->ddev);
dmcu = adev->dm.dc->res_pool->dmcu;

5
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
View File

@ -307,8 +307,6 @@ static int hibmc_load(struct drm_device *dev)
/* reset all the states of crtc/plane/encoder/connector */
drm_mode_config_reset(dev);
drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
return 0;
err:
@ -355,6 +353,9 @@ static int hibmc_pci_probe(struct pci_dev *pdev,
ret);
goto err_unload;
}
drm_fbdev_generic_setup(dev, dev->mode_config.preferred_depth);
return 0;
err_unload:

11
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -3822,6 +3822,17 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
return true;
}
unsigned int
intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
{
int x = 0, y = 0;
intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
plane_state->color_plane[0].offset, 0);
return y;
}
static int skl_check_main_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev);

1
drivers/gpu/drm/i915/display/intel_display.h
View File

@ -608,6 +608,7 @@ unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);

32
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@ -47,19 +47,6 @@
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
/*
* In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
* frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
* origin so the x and y offsets can actually fit the registers. As a
* consequence, the fence doesn't really start exactly at the display plane
* address we program because it starts at the real start of the buffer, so we
* have to take this into consideration here.
*/
static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
{
return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
}
/*
* For SKL+, the plane source size used by the hardware is based on the value we
* write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
@ -141,7 +128,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
fbc_ctl2 |= FBC_CTL_CPU_FENCE;
intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2);
intel_de_write(dev_priv, FBC_FENCE_OFF,
params->crtc.fence_y_offset);
params->fence_y_offset);
}
/* enable it... */
@ -175,7 +162,7 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
if (params->fence_id >= 0) {
dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
intel_de_write(dev_priv, DPFC_FENCE_YOFF,
params->crtc.fence_y_offset);
params->fence_y_offset);
} else {
intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0);
}
@ -243,7 +230,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | params->fence_id);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
params->crtc.fence_y_offset);
params->fence_y_offset);
}
} else {
if (IS_GEN(dev_priv, 6)) {
@ -253,7 +240,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
}
intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF,
params->crtc.fence_y_offset);
params->fence_y_offset);
/* enable it... */
intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
@ -320,7 +307,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | params->fence_id);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET,
params->crtc.fence_y_offset);
params->fence_y_offset);
} else if (dev_priv->ggtt.num_fences) {
intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0);
intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0);
@ -631,8 +618,8 @@ static bool rotation_is_valid(struct drm_i915_private *dev_priv,
/*
* For some reason, the hardware tracking starts looking at whatever we
* programmed as the display plane base address register. It does not look at
* the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
* variables instead of just looking at the pipe/plane size.
* the X and Y offset registers. That's why we include the src x/y offsets
* instead of just looking at the plane size.
*/
static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
{
@ -705,7 +692,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
cache->plane.adjusted_x = plane_state->color_plane[0].x;
cache->plane.adjusted_y = plane_state->color_plane[0].y;
cache->plane.y = plane_state->uapi.src.y1 >> 16;
cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
@ -713,6 +699,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->fb.stride = fb->pitches[0];
cache->fb.modifier = fb->modifier;
cache->fence_y_offset = intel_plane_fence_y_offset(plane_state);
drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE &&
!plane_state->vma->fence);
@ -883,10 +871,10 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
memset(params, 0, sizeof(*params));
params->fence_id = cache->fence_id;
params->fence_y_offset = cache->fence_y_offset;
params->crtc.pipe = crtc->pipe;
params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
params->fb.format = cache->fb.format;
params->fb.stride = cache->fb.stride;

12
drivers/gpu/drm/i915/gt/intel_context.c
View File

@ -204,25 +204,25 @@ static int __ring_active(struct intel_ring *ring)
{
int err;
err = i915_active_acquire(&ring->vma->active);
err = intel_ring_pin(ring);
if (err)
return err;
err = intel_ring_pin(ring);
err = i915_active_acquire(&ring->vma->active);
if (err)
goto err_active;
goto err_pin;
return 0;
err_active:
i915_active_release(&ring->vma->active);
err_pin:
intel_ring_unpin(ring);
return err;
}
static void __ring_retire(struct intel_ring *ring)
{
intel_ring_unpin(ring);
i915_active_release(&ring->vma->active);
intel_ring_unpin(ring);
}
__i915_active_call

2
drivers/gpu/drm/i915/i915_debugfs.c
View File

@ -230,7 +230,7 @@ static int per_file_stats(int id, void *ptr, void *data)
struct file_stats *stats = data;
struct i915_vma *vma;
if (!kref_get_unless_zero(&obj->base.refcount))
if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount))
return 0;
stats->count++;

6
drivers/gpu/drm/i915/i915_drv.h
View File

@ -410,8 +410,6 @@ struct intel_fbc {
int adjusted_x;
int adjusted_y;
int y;
u16 pixel_blend_mode;
} plane;
@ -420,6 +418,8 @@ struct intel_fbc {
unsigned int stride;
u64 modifier;
} fb;
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
s8 fence_id;
} state_cache;
@ -435,7 +435,6 @@ struct intel_fbc {
struct {
enum pipe pipe;
enum i9xx_plane_id i9xx_plane;
unsigned int fence_y_offset;
} crtc;
struct {
@ -444,6 +443,7 @@ struct intel_fbc {
} fb;
int cfb_size;
unsigned int fence_y_offset;
u16 gen9_wa_cfb_stride;
s8 fence_id;
bool plane_visible;

15
drivers/gpu/drm/i915/i915_vma.c
View File

@ -104,6 +104,7 @@ vma_create(struct drm_i915_gem_object *obj,
struct i915_address_space *vm,
const struct i915_ggtt_view *view)
{
struct i915_vma *pos = ERR_PTR(-E2BIG);
struct i915_vma *vma;
struct rb_node *rb, **p;
@ -184,7 +185,6 @@ vma_create(struct drm_i915_gem_object *obj,
rb = NULL;
p = &obj->vma.tree.rb_node;
while (*p) {
struct i915_vma *pos;
long cmp;
rb = *p;
@ -196,16 +196,12 @@ vma_create(struct drm_i915_gem_object *obj,
* and dispose of ours.
*/
cmp = i915_vma_compare(pos, vm, view);
if (cmp == 0) {
spin_unlock(&obj->vma.lock);
i915_vma_free(vma);
return pos;
}
if (cmp < 0)
p = &rb->rb_right;
else
else if (cmp > 0)
p = &rb->rb_left;
else
goto err_unlock;
}
rb_link_node(&vma->obj_node, rb, p);
rb_insert_color(&vma->obj_node, &obj->vma.tree);
@ -228,8 +224,9 @@ vma_create(struct drm_i915_gem_object *obj,
err_unlock:
spin_unlock(&obj->vma.lock);
err_vma:
i915_vm_put(vm);
i915_vma_free(vma);
return ERR_PTR(-E2BIG);
return pos;
}
static struct i915_vma *

2
drivers/gpu/drm/mediatek/Kconfig
View File

@ -6,12 +6,12 @@ config DRM_MEDIATEK
depends on COMMON_CLK
depends on HAVE_ARM_SMCCC
depends on OF
depends on MTK_MMSYS
select DRM_GEM_CMA_HELPER
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL
select MEMORY
select MTK_MMSYS
select MTK_SMI
select VIDEOMODE_HELPERS
help

8
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
View File

@ -193,7 +193,6 @@ static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
int ret;
int i;
DRM_DEBUG_DRIVER("%s\n", __func__);
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk);
if (ret) {
@ -213,7 +212,6 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
{
int i;
DRM_DEBUG_DRIVER("%s\n", __func__);
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
}
@ -258,7 +256,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
int ret;
int i;
DRM_DEBUG_DRIVER("%s\n", __func__);
if (WARN_ON(!crtc->state))
return -EINVAL;
@ -299,7 +296,6 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
goto err_mutex_unprepare;
}
DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
mtk_crtc->ddp_comp[i]->id,
@ -349,7 +345,6 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
struct drm_crtc *crtc = &mtk_crtc->base;
int i;
DRM_DEBUG_DRIVER("%s\n", __func__);
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
if (i == 1)
@ -831,7 +826,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
mtk_crtc->cmdq_client =
cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base),
cmdq_mbox_create(mtk_crtc->mmsys_dev,
drm_crtc_index(&mtk_crtc->base),
2000);
if (IS_ERR(mtk_crtc->cmdq_client)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",

6
drivers/gpu/drm/mediatek/mtk_drm_drv.c
View File

@ -444,7 +444,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (!private)
return -ENOMEM;
private->data = of_device_get_match_data(dev);
private->mmsys_dev = dev->parent;
if (!private->mmsys_dev) {
dev_err(dev, "Failed to get MMSYS device\n");
@ -514,7 +513,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
goto err_node;
}
ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
ret = mtk_ddp_comp_init(dev->parent, node, comp,
comp_id, NULL);
if (ret) {
of_node_put(node);
goto err_node;
@ -571,7 +571,6 @@ static int mtk_drm_sys_suspend(struct device *dev)
int ret;
ret = drm_mode_config_helper_suspend(drm);
DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
return ret;
}
@ -583,7 +582,6 @@ static int mtk_drm_sys_resume(struct device *dev)
int ret;
ret = drm_mode_config_helper_resume(drm);
DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
return ret;
}

25
drivers/gpu/drm/mediatek/mtk_drm_plane.c
View File

@ -164,6 +164,16 @@ static int mtk_plane_atomic_check(struct drm_plane *plane,
true, true);
}
static void mtk_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct mtk_plane_state *state = to_mtk_plane_state(plane->state);
state->pending.enable = false;
wmb(); /* Make sure the above parameter is set before update */
state->pending.dirty = true;
}
static void mtk_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
@ -178,6 +188,11 @@ static void mtk_plane_atomic_update(struct drm_plane *plane,
if (!crtc || WARN_ON(!fb))
return;
if (!plane->state->visible) {
mtk_plane_atomic_disable(plane, old_state);
return;
}
gem = fb->obj[0];
mtk_gem = to_mtk_gem_obj(gem);
addr = mtk_gem->dma_addr;
@ -200,16 +215,6 @@ static void mtk_plane_atomic_update(struct drm_plane *plane,
state->pending.dirty = true;
}
static void mtk_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct mtk_plane_state *state = to_mtk_plane_state(plane->state);
state->pending.enable = false;
wmb(); /* Make sure the above parameter is set before update */
state->pending.dirty = true;
}
static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
.prepare_fb = drm_gem_fb_prepare_fb,
.atomic_check = mtk_plane_atomic_check,

5
drivers/gpu/drm/mediatek/mtk_dsi.c
View File

@ -316,10 +316,7 @@ static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
{
u32 tmp_reg1;
tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
}
static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)

12
drivers/gpu/drm/mediatek/mtk_hdmi.c
View File

@ -1630,8 +1630,6 @@ static int mtk_hdmi_audio_startup(struct device *dev, void *data)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
mtk_hdmi_audio_enable(hdmi);
return 0;
@ -1641,8 +1639,6 @@ static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
mtk_hdmi_audio_disable(hdmi);
}
@ -1651,8 +1647,6 @@ mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
dev_dbg(dev, "%s(%d)\n", __func__, enable);
if (enable)
mtk_hdmi_hw_aud_mute(hdmi);
else
@ -1665,8 +1659,6 @@ static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
{
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
dev_dbg(dev, "%s\n", __func__);
memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
return 0;
@ -1766,7 +1758,6 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
goto err_bridge_remove;
}
dev_dbg(dev, "mediatek hdmi probe success\n");
return 0;
err_bridge_remove:
@ -1789,7 +1780,7 @@ static int mtk_hdmi_suspend(struct device *dev)
struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
mtk_hdmi_clk_disable_audio(hdmi);
dev_dbg(dev, "hdmi suspend success!\n");
return 0;
}
@ -1804,7 +1795,6 @@ static int mtk_hdmi_resume(struct device *dev)
return ret;
}
dev_dbg(dev, "hdmi resume success!\n");
return 0;
}
#endif

52
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
View File

@ -107,60 +107,10 @@
#define RGS_HDMITX_5T1_EDG (0xf << 4)
#define RGS_HDMITX_PLUG_TST BIT(0)
static const u8 PREDIV[3][4] = {
{0x0, 0x0, 0x0, 0x0}, /* 27Mhz */
{0x1, 0x1, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x1, 0x1, 0x1} /* 148Mhz */
};
static const u8 TXDIV[3][4] = {
{0x3, 0x3, 0x3, 0x2}, /* 27Mhz */
{0x2, 0x1, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x0, 0x0, 0x0} /* 148Mhz */
};
static const u8 FBKSEL[3][4] = {
{0x1, 0x1, 0x1, 0x1}, /* 27Mhz */
{0x1, 0x0, 0x1, 0x1}, /* 74Mhz */
{0x1, 0x0, 0x1, 0x1} /* 148Mhz */
};
static const u8 FBKDIV[3][4] = {
{19, 24, 29, 19}, /* 27Mhz */
{19, 24, 14, 19}, /* 74Mhz */
{19, 24, 14, 19} /* 148Mhz */
};
static const u8 DIVEN[3][4] = {
{0x2, 0x1, 0x1, 0x2}, /* 27Mhz */
{0x2, 0x2, 0x2, 0x2}, /* 74Mhz */
{0x2, 0x2, 0x2, 0x2} /* 148Mhz */
};
static const u8 HTPLLBP[3][4] = {
{0xc, 0xc, 0x8, 0xc}, /* 27Mhz */
{0xc, 0xf, 0xf, 0xc}, /* 74Mhz */
{0xc, 0xf, 0xf, 0xc} /* 148Mhz */
};
static const u8 HTPLLBC[3][4] = {
{0x2, 0x3, 0x3, 0x2}, /* 27Mhz */
{0x2, 0x3, 0x3, 0x2}, /* 74Mhz */
{0x2, 0x3, 0x3, 0x2} /* 148Mhz */
};
static const u8 HTPLLBR[3][4] = {
{0x1, 0x1, 0x0, 0x1}, /* 27Mhz */
{0x1, 0x2, 0x2, 0x1}, /* 74Mhz */
{0x1, 0x2, 0x2, 0x1} /* 148Mhz */
};
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
@ -178,8 +128,6 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
dev_dbg(hdmi_phy->dev, "%s\n", __func__);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
usleep_range(100, 150);

6
drivers/gpu/drm/meson/meson_registers.h
View File

@ -261,6 +261,12 @@
#define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12)
#define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22)
#define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24)
#define VIU_OSD_BURST_LENGTH_24 (0x0 << 31 | 0x0 << 10)
#define VIU_OSD_BURST_LENGTH_32 (0x0 << 31 | 0x1 << 10)
#define VIU_OSD_BURST_LENGTH_48 (0x0 << 31 | 0x2 << 10)
#define VIU_OSD_BURST_LENGTH_64 (0x0 << 31 | 0x3 << 10)
#define VIU_OSD_BURST_LENGTH_96 (0x1 << 31 | 0x0 << 10)
#define VIU_OSD_BURST_LENGTH_128 (0x1 << 31 | 0x1 << 10)
#define VD1_IF0_GEN_REG 0x1a50
#define VD1_IF0_CANVAS0 0x1a51

11
drivers/gpu/drm/meson/meson_viu.c
View File

@ -411,13 +411,6 @@ void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv)
priv->io_base + _REG(VIU_MISC_CTRL1));
}
static inline uint32_t meson_viu_osd_burst_length_reg(uint32_t length)
{
uint32_t val = (((length & 0x80) % 24) / 12);
return (((val & 0x3) << 10) | (((val & 0x4) >> 2) << 31));
}
void meson_viu_init(struct meson_drm *priv)
{
uint32_t reg;
@ -444,9 +437,9 @@ void meson_viu_init(struct meson_drm *priv)
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
reg |= meson_viu_osd_burst_length_reg(32);
reg |= VIU_OSD_BURST_LENGTH_32;
else
reg |= meson_viu_osd_burst_length_reg(64);
reg |= VIU_OSD_BURST_LENGTH_64;
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));

3
drivers/gpu/drm/nouveau/dispnv50/disp.c
View File

@ -601,6 +601,9 @@ nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
(0x0100 << nv_crtc->index),
};
if (!nv_encoder->audio)
return;
nv_encoder->audio = false;
nvif_mthd(&disp->disp->object, 0, &args, sizeof(args));

2
drivers/gpu/drm/nouveau/nouveau_dmem.c
View File

@ -550,7 +550,7 @@ static unsigned long nouveau_dmem_migrate_copy_one(struct nouveau_drm *drm,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(dev, *dma_addr))
goto out_free_page;
if (drm->dmem->migrate.copy_func(drm, page_size(spage),
if (drm->dmem->migrate.copy_func(drm, 1,
NOUVEAU_APER_VRAM, paddr, NOUVEAU_APER_HOST, *dma_addr))
goto out_dma_unmap;
} else {

1
drivers/gpu/drm/nouveau/nouveau_svm.c
View File

@ -562,6 +562,7 @@ static int nouveau_range_fault(struct nouveau_svmm *svmm,
.end = notifier->notifier.interval_tree.last + 1,
.pfn_flags_mask = HMM_PFN_REQ_FAULT | HMM_PFN_REQ_WRITE,
.hmm_pfns = hmm_pfns,
.dev_private_owner = drm->dev,
};
struct mm_struct *mm = notifier->notifier.mm;
int ret;

4
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.c
View File

@ -118,10 +118,10 @@ g94_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry,
if (retries)
udelay(400);
/* transaction request, wait up to 1ms for it to complete */
/* transaction request, wait up to 2ms for it to complete */
nvkm_wr32(device, 0x00e4e4 + base, 0x00010000 | ctrl);
timeout = 1000;
timeout = 2000;
do {
ctrl = nvkm_rd32(device, 0x00e4e4 + base);
udelay(1);

4
drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.c
View File

@ -118,10 +118,10 @@ gm200_i2c_aux_xfer(struct nvkm_i2c_aux *obj, bool retry,
if (retries)
udelay(400);
/* transaction request, wait up to 1ms for it to complete */
/* transaction request, wait up to 2ms for it to complete */
nvkm_wr32(device, 0x00d954 + base, 0x00010000 | ctrl);
timeout = 1000;
timeout = 2000;
do {
ctrl = nvkm_rd32(device, 0x00d954 + base);
udelay(1);

7
drivers/gpu/drm/radeon/ci_dpm.c
View File

@ -5563,6 +5563,7 @@ static int ci_parse_power_table(struct radeon_device *rdev)
if (!rdev->pm.dpm.ps)
return -ENOMEM;
power_state_offset = (u8 *)state_array->states;
rdev->pm.dpm.num_ps = 0;
for (i = 0; i < state_array->ucNumEntries; i++) {
u8 *idx;
power_state = (union pplib_power_state *)power_state_offset;
@ -5572,10 +5573,8 @@ static int ci_parse_power_table(struct radeon_device *rdev)
if (!rdev->pm.power_state[i].clock_info)
return -EINVAL;
ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
if (ps == NULL) {
kfree(rdev->pm.dpm.ps);
if (ps == NULL)
return -ENOMEM;
}
rdev->pm.dpm.ps[i].ps_priv = ps;
ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
non_clock_info,
@ -5597,8 +5596,8 @@ static int ci_parse_power_table(struct radeon_device *rdev)
k++;
}
power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
rdev->pm.dpm.num_ps = i + 1;
}
rdev->pm.dpm.num_ps = state_array->ucNumEntries;
/* fill in the vce power states */
for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {