drm/i915: Work around gen7 BLT ring synchronization issues.
Previous to this commit, testing easily reproduced a failure where the seqno would apparently arrive after the IRQ associated with it, with test programs as simple as: for (;;) { glCopyPixels(0, 0, 1, 1); glFinish(); } Various workarounds we've seen for previous generations didn't work to fix this issue, so until new information comes in, replace the IRQ waits on the BLT ring with polling. Signed-off-by: Eric Anholt <eric@anholt.net> Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Keith Packard <keithp@keithp.com>
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@ -791,6 +791,17 @@ ring_add_request(struct intel_ring_buffer *ring,
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return 0;
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}
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static bool
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gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
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{
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/* The BLT ring on IVB appears to have broken synchronization
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* between the seqno write and the interrupt, so that the
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* interrupt appears first. Returning false here makes
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* i915_wait_request() do a polling loop, instead.
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*/
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return false;
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}
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static bool
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gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
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{
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@ -1557,5 +1568,8 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
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*ring = gen6_blt_ring;
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if (IS_GEN7(dev))
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ring->irq_get = gen7_blt_ring_get_irq;
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return intel_init_ring_buffer(dev, ring);
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}
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