PCI: hisi: Use generic DesignWare accessors
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in pp->dbi_base, so use those instead of doing it ourselves in the hisi driver. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -43,29 +43,17 @@ struct hisi_pcie {
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struct pcie_soc_ops *soc_ops;
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};
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static inline void hisi_pcie_apb_writel(struct hisi_pcie *hisi_pcie,
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u32 val, u32 reg)
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{
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writel(val, hisi_pcie->pp.dbi_base + reg);
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}
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static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *hisi_pcie, u32 reg)
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{
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return readl(hisi_pcie->pp.dbi_base + reg);
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}
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/* HipXX PCIe host only supports 32-bit config access */
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static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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u32 reg;
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u32 reg_val;
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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reg_val = hisi_pcie_apb_readl(hisi_pcie, reg);
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reg_val = dw_pcie_readl_rc(pp, reg);
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if (size == 1)
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*val = *(u8 __force *) walker;
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@ -85,21 +73,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
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{
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u32 reg_val;
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u32 reg;
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struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp);
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void *walker = ®_val;
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walker += (where & 0x3);
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reg = where & ~0x3;
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if (size == 4)
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hisi_pcie_apb_writel(hisi_pcie, val, reg);
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dw_pcie_writel_rc(pp, reg, val);
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else if (size == 2) {
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reg_val = hisi_pcie_apb_readl(hisi_pcie, reg);
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reg_val = dw_pcie_readl_rc(pp, reg);
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*(u16 __force *) walker = val;
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hisi_pcie_apb_writel(hisi_pcie, reg_val, reg);
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dw_pcie_writel_rc(pp, reg, reg_val);
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} else if (size == 1) {
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reg_val = hisi_pcie_apb_readl(hisi_pcie, reg);
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reg_val = dw_pcie_readl_rc(pp, reg);
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*(u8 __force *) walker = val;
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hisi_pcie_apb_writel(hisi_pcie, reg_val, reg);
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dw_pcie_writel_rc(pp, reg, reg_val);
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} else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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@ -118,10 +105,10 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
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static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
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{
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struct pcie_port *pp = &hisi_pcie->pp;
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u32 val;
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val = hisi_pcie_apb_readl(hisi_pcie, PCIE_HIP06_CTRL_OFF +
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PCIE_SYS_STATE4);
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val = dw_pcie_readl_rc(pp, PCIE_HIP06_CTRL_OFF + PCIE_SYS_STATE4);
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return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
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}
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