Merge branch 'clk-actions' into clk-next
* clk-actions: clk: actions: Add S900 SoC clock support clk: actions: Add pll clock support clk: actions: Add composite clock support clk: actions: Add fixed factor clock support clk: actions: Add factor clock support clk: actions: Add divider clock support clk: actions: Add mux clock support clk: actions: Add gate clock support clk: actions: Add common clock driver support dt-bindings: clock: Add Actions S900 clock bindingshifive-unleashed-5.1
Stephen Boyd
commit
43705f5294
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@ -0,0 +1,47 @@
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* Actions S900 Clock Management Unit (CMU)
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The Actions S900 clock management unit generates and supplies clock to various
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controllers within the SoC. The clock binding described here is applicable to
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S900 SoC.
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Required Properties:
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- compatible: should be "actions,s900-cmu"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- clocks: Reference to the parent clocks ("hosc", "losc")
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- #clock-cells: should be 1.
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Each clock is assigned an identifier, and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/actions,s900-cmu.h header and can be used in device
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tree sources.
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External clocks:
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The hosc clock used as input for the plls is generated outside the SoC. It is
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expected that it is defined using standard clock bindings as "hosc".
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Actions S900 CMU also requires one more clock:
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- "losc" - internal low frequency oscillator
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Example: Clock Management Unit node:
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cmu: clock-controller@e0160000 {
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compatible = "actions,s900-cmu";
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reg = <0x0 0xe0160000 0x0 0x1000>;
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clocks = <&hosc>, <&losc>;
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#clock-cells = <1>;
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};
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Example: UART controller node that consumes clock generated by the clock
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management unit:
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uart: serial@e012a000 {
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compatible = "actions,s900-uart", "actions,owl-uart";
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reg = <0x0 0xe012a000 0x0 0x2000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART5>;
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};
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@ -279,6 +279,7 @@ config COMMON_CLK_STM32H7
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---help---
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Support for stm32h7 SoC family clocks
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source "drivers/clk/actions/Kconfig"
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/imgtec/Kconfig"
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@ -59,6 +59,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
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# please keep this section sorted lexicographically by directory path name
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obj-y += actions/
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obj-$(CONFIG_COMMON_CLK_AT91) += at91/
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obj-$(CONFIG_ARCH_ARTPEC) += axis/
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obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
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@ -0,0 +1,14 @@
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config CLK_ACTIONS
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bool "Clock driver for Actions Semi SoCs"
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depends on ARCH_ACTIONS || COMPILE_TEST
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default ARCH_ACTIONS
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if CLK_ACTIONS
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# SoC Drivers
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config CLK_OWL_S900
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bool "Support for the Actions Semi OWL S900 clocks"
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depends on (ARM64 && ARCH_ACTIONS) || COMPILE_TEST
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default ARM64 && ARCH_ACTIONS
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endif
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@ -0,0 +1,12 @@
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obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o
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clk-owl-y += owl-common.o
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clk-owl-y += owl-gate.o
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clk-owl-y += owl-mux.o
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clk-owl-y += owl-divider.o
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clk-owl-y += owl-factor.o
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clk-owl-y += owl-composite.o
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clk-owl-y += owl-pll.o
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# SoC support
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obj-$(CONFIG_CLK_OWL_S900) += owl-s900.o
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@ -0,0 +1,89 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL common clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "owl-common.h"
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static const struct regmap_config owl_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x00cc,
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.fast_io = true,
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};
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static void owl_clk_set_regmap(const struct owl_clk_desc *desc,
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struct regmap *regmap)
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{
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int i;
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struct owl_clk_common *clks;
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for (i = 0; i < desc->num_clks; i++) {
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clks = desc->clks[i];
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if (!clks)
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continue;
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clks->regmap = regmap;
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}
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}
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int owl_clk_regmap_init(struct platform_device *pdev,
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const struct owl_clk_desc *desc)
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{
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void __iomem *base;
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struct regmap *regmap;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base, &owl_regmap_config);
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if (IS_ERR(regmap)) {
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pr_err("failed to init regmap\n");
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return PTR_ERR(regmap);
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}
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owl_clk_set_regmap(desc, regmap);
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return 0;
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}
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int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks)
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{
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int i, ret;
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struct clk_hw *hw;
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for (i = 0; i < hw_clks->num; i++) {
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hw = hw_clks->hws[i];
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if (IS_ERR_OR_NULL(hw))
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continue;
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ret = devm_clk_hw_register(dev, hw);
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if (ret) {
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dev_err(dev, "Couldn't register clock %d - %s\n",
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i, hw->init->name);
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return ret;
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}
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_clks);
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if (ret)
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dev_err(dev, "Failed to add clock provider\n");
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return ret;
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}
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@ -0,0 +1,41 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL common clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#ifndef _OWL_COMMON_H_
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#define _OWL_COMMON_H_
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#include <linux/clk-provider.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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struct device_node;
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struct owl_clk_common {
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struct regmap *regmap;
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struct clk_hw hw;
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};
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struct owl_clk_desc {
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struct owl_clk_common **clks;
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unsigned long num_clks;
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struct clk_hw_onecell_data *hw_clks;
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};
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static inline struct owl_clk_common *
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hw_to_owl_clk_common(const struct clk_hw *hw)
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{
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return container_of(hw, struct owl_clk_common, hw);
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}
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int owl_clk_regmap_init(struct platform_device *pdev,
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const struct owl_clk_desc *desc);
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int owl_clk_probe(struct device *dev, struct clk_hw_onecell_data *hw_clks);
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#endif /* _OWL_COMMON_H_ */
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@ -0,0 +1,199 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
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// OWL composite clock driver
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//
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// Copyright (c) 2014 Actions Semi Inc.
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// Author: David Liu <liuwei@actions-semi.com>
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//
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// Copyright (c) 2018 Linaro Ltd.
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// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include "owl-composite.h"
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static u8 owl_comp_get_parent(struct clk_hw *hw)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_mux_helper_get_parent(&comp->common, &comp->mux_hw);
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}
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static int owl_comp_set_parent(struct clk_hw *hw, u8 index)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_mux_helper_set_parent(&comp->common, &comp->mux_hw, index);
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}
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static void owl_comp_disable(struct clk_hw *hw)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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struct owl_clk_common *common = &comp->common;
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owl_gate_set(common, &comp->gate_hw, false);
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}
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static int owl_comp_enable(struct clk_hw *hw)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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struct owl_clk_common *common = &comp->common;
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owl_gate_set(common, &comp->gate_hw, true);
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return 0;
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}
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static int owl_comp_is_enabled(struct clk_hw *hw)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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struct owl_clk_common *common = &comp->common;
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return owl_gate_clk_is_enabled(common, &comp->gate_hw);
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}
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static long owl_comp_div_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
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rate, parent_rate);
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}
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static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_divider_helper_recalc_rate(&comp->common, &comp->rate.div_hw,
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parent_rate);
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}
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static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_divider_helper_set_rate(&comp->common, &comp->rate.div_hw,
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rate, parent_rate);
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}
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static long owl_comp_fact_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_factor_helper_round_rate(&comp->common,
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&comp->rate.factor_hw,
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rate, parent_rate);
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}
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static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_factor_helper_recalc_rate(&comp->common,
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&comp->rate.factor_hw,
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parent_rate);
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}
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static int owl_comp_fact_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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return owl_factor_helper_set_rate(&comp->common,
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&comp->rate.factor_hw,
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rate, parent_rate);
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}
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static long owl_comp_fix_fact_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
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return comp->fix_fact_ops->round_rate(&fix_fact_hw->hw, rate, parent_rate);
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}
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static unsigned long owl_comp_fix_fact_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct owl_composite *comp = hw_to_owl_comp(hw);
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struct clk_fixed_factor *fix_fact_hw = &comp->rate.fix_fact_hw;
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return comp->fix_fact_ops->recalc_rate(&fix_fact_hw->hw, parent_rate);
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}
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static int owl_comp_fix_fact_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* We must report success but we can do so unconditionally because
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* owl_comp_fix_fact_round_rate returns values that ensure this call is
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* a nop.
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*/
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return 0;
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}
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const struct clk_ops owl_comp_div_ops = {
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/* mux_ops */
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.get_parent = owl_comp_get_parent,
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.set_parent = owl_comp_set_parent,
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/* gate_ops */
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.disable = owl_comp_disable,
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.enable = owl_comp_enable,
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.is_enabled = owl_comp_is_enabled,
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/* div_ops */
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.round_rate = owl_comp_div_round_rate,
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.recalc_rate = owl_comp_div_recalc_rate,
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.set_rate = owl_comp_div_set_rate,
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};
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const struct clk_ops owl_comp_fact_ops = {
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/* mux_ops */
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.get_parent = owl_comp_get_parent,
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.set_parent = owl_comp_set_parent,
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/* gate_ops */
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.disable = owl_comp_disable,
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.enable = owl_comp_enable,
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.is_enabled = owl_comp_is_enabled,
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/* fact_ops */
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.round_rate = owl_comp_fact_round_rate,
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.recalc_rate = owl_comp_fact_recalc_rate,
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.set_rate = owl_comp_fact_set_rate,
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};
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const struct clk_ops owl_comp_fix_fact_ops = {
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/* gate_ops */
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.disable = owl_comp_disable,
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.enable = owl_comp_enable,
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.is_enabled = owl_comp_is_enabled,
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/* fix_fact_ops */
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.round_rate = owl_comp_fix_fact_round_rate,
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.recalc_rate = owl_comp_fix_fact_recalc_rate,
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.set_rate = owl_comp_fix_fact_set_rate,
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};
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const struct clk_ops owl_comp_pass_ops = {
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/* mux_ops */
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.get_parent = owl_comp_get_parent,
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.set_parent = owl_comp_set_parent,
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/* gate_ops */
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.disable = owl_comp_disable,
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.enable = owl_comp_enable,
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.is_enabled = owl_comp_is_enabled,
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};
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@ -0,0 +1,124 @@
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// SPDX-License-Identifier: GPL-2.0+
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//
|
||||
// OWL composite clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
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|
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#ifndef _OWL_COMPOSITE_H_
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#define _OWL_COMPOSITE_H_
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#include "owl-common.h"
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#include "owl-mux.h"
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#include "owl-gate.h"
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#include "owl-factor.h"
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#include "owl-fixed-factor.h"
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#include "owl-divider.h"
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union owl_rate {
|
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struct owl_divider_hw div_hw;
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struct owl_factor_hw factor_hw;
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struct clk_fixed_factor fix_fact_hw;
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};
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|
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struct owl_composite {
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struct owl_mux_hw mux_hw;
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struct owl_gate_hw gate_hw;
|
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union owl_rate rate;
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|
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const struct clk_ops *fix_fact_ops;
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|
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struct owl_clk_common common;
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};
|
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|
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#define OWL_COMP_DIV(_struct, _name, _parent, \
|
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_mux, _gate, _div, _flags) \
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struct owl_composite _struct = { \
|
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.mux_hw = _mux, \
|
||||
.gate_hw = _gate, \
|
||||
.rate.div_hw = _div, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&owl_comp_div_ops,\
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \
|
||||
_gate, _div, _flags) \
|
||||
struct owl_composite _struct = { \
|
||||
.gate_hw = _gate, \
|
||||
.rate.div_hw = _div, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_comp_div_ops,\
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define OWL_COMP_FACTOR(_struct, _name, _parent, \
|
||||
_mux, _gate, _factor, _flags) \
|
||||
struct owl_composite _struct = { \
|
||||
.mux_hw = _mux, \
|
||||
.gate_hw = _gate, \
|
||||
.rate.factor_hw = _factor, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&owl_comp_fact_ops,\
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \
|
||||
_gate, _mul, _div, _flags) \
|
||||
struct owl_composite _struct = { \
|
||||
.gate_hw = _gate, \
|
||||
.rate.fix_fact_hw.mult = _mul, \
|
||||
.rate.fix_fact_hw.div = _div, \
|
||||
.fix_fact_ops = &clk_fixed_factor_ops, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_comp_fix_fact_ops,\
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define OWL_COMP_PASS(_struct, _name, _parent, \
|
||||
_mux, _gate, _flags) \
|
||||
struct owl_composite _struct = { \
|
||||
.mux_hw = _mux, \
|
||||
.gate_hw = _gate, \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parent, \
|
||||
&owl_comp_pass_ops,\
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static inline struct owl_composite *hw_to_owl_comp(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_composite, common);
|
||||
}
|
||||
|
||||
extern const struct clk_ops owl_comp_div_ops;
|
||||
extern const struct clk_ops owl_comp_fact_ops;
|
||||
extern const struct clk_ops owl_comp_fix_fact_ops;
|
||||
extern const struct clk_ops owl_comp_pass_ops;
|
||||
extern const struct clk_ops clk_fixed_factor_ops;
|
||||
|
||||
#endif /* _OWL_COMPOSITE_H_ */
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL divider clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "owl-divider.h"
|
||||
|
||||
long owl_divider_helper_round_rate(struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
return divider_round_rate(&common->hw, rate, parent_rate,
|
||||
div_hw->table, div_hw->width,
|
||||
div_hw->div_flags);
|
||||
}
|
||||
|
||||
static long owl_divider_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct owl_divider *div = hw_to_owl_divider(hw);
|
||||
|
||||
return owl_divider_helper_round_rate(&div->common, &div->div_hw,
|
||||
rate, parent_rate);
|
||||
}
|
||||
|
||||
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned int reg;
|
||||
|
||||
regmap_read(common->regmap, div_hw->reg, ®);
|
||||
val = reg >> div_hw->shift;
|
||||
val &= (1 << div_hw->width) - 1;
|
||||
|
||||
return divider_recalc_rate(&common->hw, parent_rate,
|
||||
val, div_hw->table,
|
||||
div_hw->div_flags,
|
||||
div_hw->width);
|
||||
}
|
||||
|
||||
static unsigned long owl_divider_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_divider *div = hw_to_owl_divider(hw);
|
||||
|
||||
return owl_divider_helper_recalc_rate(&div->common,
|
||||
&div->div_hw, parent_rate);
|
||||
}
|
||||
|
||||
int owl_divider_helper_set_rate(const struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long val;
|
||||
unsigned int reg;
|
||||
|
||||
val = divider_get_val(rate, parent_rate, div_hw->table,
|
||||
div_hw->width, 0);
|
||||
|
||||
regmap_read(common->regmap, div_hw->reg, ®);
|
||||
reg &= ~GENMASK(div_hw->width + div_hw->shift - 1, div_hw->shift);
|
||||
|
||||
regmap_write(common->regmap, div_hw->reg,
|
||||
reg | (val << div_hw->shift));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_divider_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_divider *div = hw_to_owl_divider(hw);
|
||||
|
||||
return owl_divider_helper_set_rate(&div->common, &div->div_hw,
|
||||
rate, parent_rate);
|
||||
}
|
||||
|
||||
const struct clk_ops owl_divider_ops = {
|
||||
.recalc_rate = owl_divider_recalc_rate,
|
||||
.round_rate = owl_divider_round_rate,
|
||||
.set_rate = owl_divider_set_rate,
|
||||
};
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL divider clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_DIVIDER_H_
|
||||
#define _OWL_DIVIDER_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
struct owl_divider_hw {
|
||||
u32 reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 div_flags;
|
||||
struct clk_div_table *table;
|
||||
};
|
||||
|
||||
struct owl_divider {
|
||||
struct owl_divider_hw div_hw;
|
||||
struct owl_clk_common common;
|
||||
};
|
||||
|
||||
#define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \
|
||||
{ \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.div_flags = _div_flags, \
|
||||
.table = _table, \
|
||||
}
|
||||
|
||||
#define OWL_DIVIDER(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _table, _div_flags, _flags) \
|
||||
struct owl_divider _struct = { \
|
||||
.div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
|
||||
_div_flags, _table), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_divider_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static inline struct owl_divider *hw_to_owl_divider(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_divider, common);
|
||||
}
|
||||
|
||||
long owl_divider_helper_round_rate(struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long rate,
|
||||
unsigned long *parent_rate);
|
||||
|
||||
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long parent_rate);
|
||||
|
||||
int owl_divider_helper_set_rate(const struct owl_clk_common *common,
|
||||
const struct owl_divider_hw *div_hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
|
||||
extern const struct clk_ops owl_divider_ops;
|
||||
|
||||
#endif /* _OWL_DIVIDER_H_ */
|
||||
|
|
@ -0,0 +1,222 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL factor clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "owl-factor.h"
|
||||
|
||||
static unsigned int _get_table_maxval(const struct clk_factor_table *table)
|
||||
{
|
||||
unsigned int maxval = 0;
|
||||
const struct clk_factor_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++)
|
||||
if (clkt->val > maxval)
|
||||
maxval = clkt->val;
|
||||
return maxval;
|
||||
}
|
||||
|
||||
static int _get_table_div_mul(const struct clk_factor_table *table,
|
||||
unsigned int val, unsigned int *mul, unsigned int *div)
|
||||
{
|
||||
const struct clk_factor_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++) {
|
||||
if (clkt->val == val) {
|
||||
*mul = clkt->mul;
|
||||
*div = clkt->div;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int _get_table_val(const struct clk_factor_table *table,
|
||||
unsigned long rate, unsigned long parent_rate)
|
||||
{
|
||||
const struct clk_factor_table *clkt;
|
||||
int val = -1;
|
||||
u64 calc_rate;
|
||||
|
||||
for (clkt = table; clkt->div; clkt++) {
|
||||
calc_rate = parent_rate * clkt->mul;
|
||||
do_div(calc_rate, clkt->div);
|
||||
|
||||
if ((unsigned long)calc_rate <= rate) {
|
||||
val = clkt->val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (val == -1)
|
||||
val = _get_table_maxval(table);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static int clk_val_best(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *best_parent_rate)
|
||||
{
|
||||
struct owl_factor *factor = hw_to_owl_factor(hw);
|
||||
struct owl_factor_hw *factor_hw = &factor->factor_hw;
|
||||
const struct clk_factor_table *clkt = factor_hw->table;
|
||||
unsigned long parent_rate, try_parent_rate, best = 0, cur_rate;
|
||||
unsigned long parent_rate_saved = *best_parent_rate;
|
||||
int bestval = 0;
|
||||
|
||||
if (!rate)
|
||||
rate = 1;
|
||||
|
||||
if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
|
||||
parent_rate = *best_parent_rate;
|
||||
bestval = _get_table_val(clkt, rate, parent_rate);
|
||||
return bestval;
|
||||
}
|
||||
|
||||
for (clkt = factor_hw->table; clkt->div; clkt++) {
|
||||
try_parent_rate = rate * clkt->div / clkt->mul;
|
||||
|
||||
if (try_parent_rate == parent_rate_saved) {
|
||||
pr_debug("%s: [%d %d %d] found try_parent_rate %ld\n",
|
||||
__func__, clkt->val, clkt->mul, clkt->div,
|
||||
try_parent_rate);
|
||||
/*
|
||||
* It's the most ideal case if the requested rate can be
|
||||
* divided from parent clock without any need to change
|
||||
* parent rate, so return the divider immediately.
|
||||
*/
|
||||
*best_parent_rate = parent_rate_saved;
|
||||
return clkt->val;
|
||||
}
|
||||
|
||||
parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
|
||||
try_parent_rate);
|
||||
cur_rate = DIV_ROUND_UP(parent_rate, clkt->div) * clkt->mul;
|
||||
if (cur_rate <= rate && cur_rate > best) {
|
||||
bestval = clkt->val;
|
||||
best = cur_rate;
|
||||
*best_parent_rate = parent_rate;
|
||||
}
|
||||
}
|
||||
|
||||
if (!bestval) {
|
||||
bestval = _get_table_maxval(clkt);
|
||||
*best_parent_rate = clk_hw_round_rate(
|
||||
clk_hw_get_parent(hw), 1);
|
||||
}
|
||||
|
||||
return bestval;
|
||||
}
|
||||
|
||||
long owl_factor_helper_round_rate(struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
const struct clk_factor_table *clkt = factor_hw->table;
|
||||
unsigned int val, mul = 0, div = 1;
|
||||
|
||||
val = clk_val_best(&common->hw, rate, parent_rate);
|
||||
_get_table_div_mul(clkt, val, &mul, &div);
|
||||
|
||||
return *parent_rate * mul / div;
|
||||
}
|
||||
|
||||
static long owl_factor_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct owl_factor *factor = hw_to_owl_factor(hw);
|
||||
struct owl_factor_hw *factor_hw = &factor->factor_hw;
|
||||
|
||||
return owl_factor_helper_round_rate(&factor->common, factor_hw,
|
||||
rate, parent_rate);
|
||||
}
|
||||
|
||||
unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
const struct clk_factor_table *clkt = factor_hw->table;
|
||||
unsigned long long int rate;
|
||||
u32 reg, val, mul, div;
|
||||
|
||||
div = 0;
|
||||
mul = 0;
|
||||
|
||||
regmap_read(common->regmap, factor_hw->reg, ®);
|
||||
|
||||
val = reg >> factor_hw->shift;
|
||||
val &= div_mask(factor_hw);
|
||||
|
||||
_get_table_div_mul(clkt, val, &mul, &div);
|
||||
if (!div) {
|
||||
WARN(!(factor_hw->fct_flags & CLK_DIVIDER_ALLOW_ZERO),
|
||||
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
|
||||
__clk_get_name(common->hw.clk));
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
rate = (unsigned long long int)parent_rate * mul;
|
||||
do_div(rate, div);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long owl_factor_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_factor *factor = hw_to_owl_factor(hw);
|
||||
struct owl_factor_hw *factor_hw = &factor->factor_hw;
|
||||
struct owl_clk_common *common = &factor->common;
|
||||
|
||||
return owl_factor_helper_recalc_rate(common, factor_hw, parent_rate);
|
||||
}
|
||||
|
||||
int owl_factor_helper_set_rate(const struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
u32 val, reg;
|
||||
|
||||
val = _get_table_val(factor_hw->table, rate, parent_rate);
|
||||
|
||||
if (val > div_mask(factor_hw))
|
||||
val = div_mask(factor_hw);
|
||||
|
||||
regmap_read(common->regmap, factor_hw->reg, ®);
|
||||
|
||||
reg &= ~(div_mask(factor_hw) << factor_hw->shift);
|
||||
reg |= val << factor_hw->shift;
|
||||
|
||||
regmap_write(common->regmap, factor_hw->reg, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_factor_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_factor *factor = hw_to_owl_factor(hw);
|
||||
struct owl_factor_hw *factor_hw = &factor->factor_hw;
|
||||
struct owl_clk_common *common = &factor->common;
|
||||
|
||||
return owl_factor_helper_set_rate(common, factor_hw,
|
||||
rate, parent_rate);
|
||||
}
|
||||
|
||||
const struct clk_ops owl_factor_ops = {
|
||||
.round_rate = owl_factor_round_rate,
|
||||
.recalc_rate = owl_factor_recalc_rate,
|
||||
.set_rate = owl_factor_set_rate,
|
||||
};
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL factor clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_FACTOR_H_
|
||||
#define _OWL_FACTOR_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
struct clk_factor_table {
|
||||
unsigned int val;
|
||||
unsigned int mul;
|
||||
unsigned int div;
|
||||
};
|
||||
|
||||
struct owl_factor_hw {
|
||||
u32 reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 fct_flags;
|
||||
struct clk_factor_table *table;
|
||||
};
|
||||
|
||||
struct owl_factor {
|
||||
struct owl_factor_hw factor_hw;
|
||||
struct owl_clk_common common;
|
||||
};
|
||||
|
||||
#define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \
|
||||
{ \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.fct_flags = _fct_flags, \
|
||||
.table = _table, \
|
||||
}
|
||||
|
||||
#define OWL_FACTOR(_struct, _name, _parent, _reg, \
|
||||
_shift, _width, _table, _fct_flags, _flags) \
|
||||
struct owl_factor _struct = { \
|
||||
.factor_hw = OWL_FACTOR_HW(_reg, _shift, \
|
||||
_width, _fct_flags, _table), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_factor_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define div_mask(d) ((1 << ((d)->width)) - 1)
|
||||
|
||||
static inline struct owl_factor *hw_to_owl_factor(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_factor, common);
|
||||
}
|
||||
|
||||
long owl_factor_helper_round_rate(struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long rate,
|
||||
unsigned long *parent_rate);
|
||||
|
||||
unsigned long owl_factor_helper_recalc_rate(struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long parent_rate);
|
||||
|
||||
int owl_factor_helper_set_rate(const struct owl_clk_common *common,
|
||||
const struct owl_factor_hw *factor_hw,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate);
|
||||
|
||||
extern const struct clk_ops owl_factor_ops;
|
||||
|
||||
#endif /* _OWL_FACTOR_H_ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL fixed factor clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_FIXED_FACTOR_H_
|
||||
#define _OWL_FIXED_FACTOR_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
#define OWL_FIX_FACT(_struct, _name, _parent, _mul, _div, _flags) \
|
||||
struct clk_fixed_factor _struct = { \
|
||||
.mult = _mul, \
|
||||
.div = _div, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&clk_fixed_factor_ops, \
|
||||
_flags), \
|
||||
}
|
||||
|
||||
extern const struct clk_ops clk_fixed_factor_ops;
|
||||
|
||||
#endif /* _OWL_FIXED_FACTOR_H_ */
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL gate clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "owl-gate.h"
|
||||
|
||||
void owl_gate_set(const struct owl_clk_common *common,
|
||||
const struct owl_gate_hw *gate_hw, bool enable)
|
||||
{
|
||||
int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
|
||||
u32 reg;
|
||||
|
||||
set ^= enable;
|
||||
|
||||
regmap_read(common->regmap, gate_hw->reg, ®);
|
||||
|
||||
if (set)
|
||||
reg |= BIT(gate_hw->bit_idx);
|
||||
else
|
||||
reg &= ~BIT(gate_hw->bit_idx);
|
||||
|
||||
regmap_write(common->regmap, gate_hw->reg, reg);
|
||||
}
|
||||
|
||||
static void owl_gate_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_gate *gate = hw_to_owl_gate(hw);
|
||||
struct owl_clk_common *common = &gate->common;
|
||||
|
||||
owl_gate_set(common, &gate->gate_hw, false);
|
||||
}
|
||||
|
||||
static int owl_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_gate *gate = hw_to_owl_gate(hw);
|
||||
struct owl_clk_common *common = &gate->common;
|
||||
|
||||
owl_gate_set(common, &gate->gate_hw, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
|
||||
const struct owl_gate_hw *gate_hw)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
regmap_read(common->regmap, gate_hw->reg, ®);
|
||||
|
||||
if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
|
||||
reg ^= BIT(gate_hw->bit_idx);
|
||||
|
||||
return !!(reg & BIT(gate_hw->bit_idx));
|
||||
}
|
||||
|
||||
static int owl_gate_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_gate *gate = hw_to_owl_gate(hw);
|
||||
struct owl_clk_common *common = &gate->common;
|
||||
|
||||
return owl_gate_clk_is_enabled(common, &gate->gate_hw);
|
||||
}
|
||||
|
||||
const struct clk_ops owl_gate_ops = {
|
||||
.disable = owl_gate_disable,
|
||||
.enable = owl_gate_enable,
|
||||
.is_enabled = owl_gate_is_enabled,
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL gate clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_GATE_H_
|
||||
#define _OWL_GATE_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
struct owl_gate_hw {
|
||||
u32 reg;
|
||||
u8 bit_idx;
|
||||
u8 gate_flags;
|
||||
};
|
||||
|
||||
struct owl_gate {
|
||||
struct owl_gate_hw gate_hw;
|
||||
struct owl_clk_common common;
|
||||
};
|
||||
|
||||
#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \
|
||||
{ \
|
||||
.reg = _reg, \
|
||||
.bit_idx = _bit_idx, \
|
||||
.gate_flags = _gate_flags, \
|
||||
}
|
||||
|
||||
#define OWL_GATE(_struct, _name, _parent, _reg, \
|
||||
_bit_idx, _gate_flags, _flags) \
|
||||
struct owl_gate _struct = { \
|
||||
.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_gate_ops, \
|
||||
_flags), \
|
||||
} \
|
||||
} \
|
||||
|
||||
#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \
|
||||
_bit_idx, _gate_flags, _flags) \
|
||||
struct owl_gate _struct = { \
|
||||
.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
|
||||
&owl_gate_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
} \
|
||||
|
||||
static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_gate, common);
|
||||
}
|
||||
|
||||
void owl_gate_set(const struct owl_clk_common *common,
|
||||
const struct owl_gate_hw *gate_hw, bool enable);
|
||||
int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
|
||||
const struct owl_gate_hw *gate_hw);
|
||||
|
||||
extern const struct clk_ops owl_gate_ops;
|
||||
|
||||
#endif /* _OWL_GATE_H_ */
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL mux clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "owl-mux.h"
|
||||
|
||||
u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
|
||||
const struct owl_mux_hw *mux_hw)
|
||||
{
|
||||
u32 reg;
|
||||
u8 parent;
|
||||
|
||||
regmap_read(common->regmap, mux_hw->reg, ®);
|
||||
parent = reg >> mux_hw->shift;
|
||||
parent &= BIT(mux_hw->width) - 1;
|
||||
|
||||
return parent;
|
||||
}
|
||||
|
||||
static u8 owl_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_mux *mux = hw_to_owl_mux(hw);
|
||||
|
||||
return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
|
||||
}
|
||||
|
||||
int owl_mux_helper_set_parent(const struct owl_clk_common *common,
|
||||
struct owl_mux_hw *mux_hw, u8 index)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
regmap_read(common->regmap, mux_hw->reg, ®);
|
||||
reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
|
||||
regmap_write(common->regmap, mux_hw->reg,
|
||||
reg | (index << mux_hw->shift));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct owl_mux *mux = hw_to_owl_mux(hw);
|
||||
|
||||
return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
|
||||
}
|
||||
|
||||
const struct clk_ops owl_mux_ops = {
|
||||
.get_parent = owl_mux_get_parent,
|
||||
.set_parent = owl_mux_set_parent,
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
};
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL mux clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_MUX_H_
|
||||
#define _OWL_MUX_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
struct owl_mux_hw {
|
||||
u32 reg;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
};
|
||||
|
||||
struct owl_mux {
|
||||
struct owl_mux_hw mux_hw;
|
||||
struct owl_clk_common common;
|
||||
};
|
||||
|
||||
#define OWL_MUX_HW(_reg, _shift, _width) \
|
||||
{ \
|
||||
.reg = _reg, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
}
|
||||
|
||||
#define OWL_MUX(_struct, _name, _parents, _reg, \
|
||||
_shift, _width, _flags) \
|
||||
struct owl_mux _struct = { \
|
||||
.mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parents, \
|
||||
&owl_mux_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
static inline struct owl_mux *hw_to_owl_mux(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_mux, common);
|
||||
}
|
||||
|
||||
u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
|
||||
const struct owl_mux_hw *mux_hw);
|
||||
int owl_mux_helper_set_parent(const struct owl_clk_common *common,
|
||||
struct owl_mux_hw *mux_hw, u8 index);
|
||||
|
||||
extern const struct clk_ops owl_mux_ops;
|
||||
|
||||
#endif /* _OWL_MUX_H_ */
|
||||
|
|
@ -0,0 +1,194 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL pll clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include "owl-pll.h"
|
||||
|
||||
static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate)
|
||||
{
|
||||
u32 mul;
|
||||
|
||||
mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq);
|
||||
if (mul < pll_hw->min_mul)
|
||||
mul = pll_hw->min_mul;
|
||||
else if (mul > pll_hw->max_mul)
|
||||
mul = pll_hw->max_mul;
|
||||
|
||||
return mul &= mul_mask(pll_hw);
|
||||
}
|
||||
|
||||
static unsigned long _get_table_rate(const struct clk_pll_table *table,
|
||||
unsigned int val)
|
||||
{
|
||||
const struct clk_pll_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->rate; clkt++)
|
||||
if (clkt->val == val)
|
||||
return clkt->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_pll_table *_get_pll_table(
|
||||
const struct clk_pll_table *table, unsigned long rate)
|
||||
{
|
||||
const struct clk_pll_table *clkt;
|
||||
|
||||
for (clkt = table; clkt->rate; clkt++) {
|
||||
if (clkt->rate == rate) {
|
||||
table = clkt;
|
||||
break;
|
||||
} else if (clkt->rate < rate)
|
||||
table = clkt;
|
||||
}
|
||||
|
||||
return table;
|
||||
}
|
||||
|
||||
static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
struct owl_pll_hw *pll_hw = &pll->pll_hw;
|
||||
const struct clk_pll_table *clkt;
|
||||
u32 mul;
|
||||
|
||||
if (pll_hw->table) {
|
||||
clkt = _get_pll_table(pll_hw->table, rate);
|
||||
return clkt->rate;
|
||||
}
|
||||
|
||||
/* fixed frequency */
|
||||
if (pll_hw->width == 0)
|
||||
return pll_hw->bfreq;
|
||||
|
||||
mul = owl_pll_calculate_mul(pll_hw, rate);
|
||||
|
||||
return pll_hw->bfreq * mul;
|
||||
}
|
||||
|
||||
static unsigned long owl_pll_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
struct owl_pll_hw *pll_hw = &pll->pll_hw;
|
||||
const struct owl_clk_common *common = &pll->common;
|
||||
u32 val;
|
||||
|
||||
if (pll_hw->table) {
|
||||
regmap_read(common->regmap, pll_hw->reg, &val);
|
||||
|
||||
val = val >> pll_hw->shift;
|
||||
val &= mul_mask(pll_hw);
|
||||
|
||||
return _get_table_rate(pll_hw->table, val);
|
||||
}
|
||||
|
||||
/* fixed frequency */
|
||||
if (pll_hw->width == 0)
|
||||
return pll_hw->bfreq;
|
||||
|
||||
regmap_read(common->regmap, pll_hw->reg, &val);
|
||||
|
||||
val = val >> pll_hw->shift;
|
||||
val &= mul_mask(pll_hw);
|
||||
|
||||
return pll_hw->bfreq * val;
|
||||
}
|
||||
|
||||
static int owl_pll_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
struct owl_pll_hw *pll_hw = &pll->pll_hw;
|
||||
const struct owl_clk_common *common = &pll->common;
|
||||
u32 reg;
|
||||
|
||||
regmap_read(common->regmap, pll_hw->reg, ®);
|
||||
|
||||
return !!(reg & BIT(pll_hw->bit_idx));
|
||||
}
|
||||
|
||||
static void owl_pll_set(const struct owl_clk_common *common,
|
||||
const struct owl_pll_hw *pll_hw, bool enable)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
regmap_read(common->regmap, pll_hw->reg, ®);
|
||||
|
||||
if (enable)
|
||||
reg |= BIT(pll_hw->bit_idx);
|
||||
else
|
||||
reg &= ~BIT(pll_hw->bit_idx);
|
||||
|
||||
regmap_write(common->regmap, pll_hw->reg, reg);
|
||||
}
|
||||
|
||||
static int owl_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
const struct owl_clk_common *common = &pll->common;
|
||||
|
||||
owl_pll_set(common, &pll->pll_hw, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void owl_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
const struct owl_clk_common *common = &pll->common;
|
||||
|
||||
owl_pll_set(common, &pll->pll_hw, false);
|
||||
}
|
||||
|
||||
static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct owl_pll *pll = hw_to_owl_pll(hw);
|
||||
struct owl_pll_hw *pll_hw = &pll->pll_hw;
|
||||
const struct owl_clk_common *common = &pll->common;
|
||||
const struct clk_pll_table *clkt;
|
||||
u32 val, reg;
|
||||
|
||||
/* fixed frequency */
|
||||
if (pll_hw->width == 0)
|
||||
return 0;
|
||||
|
||||
if (pll_hw->table) {
|
||||
clkt = _get_pll_table(pll_hw->table, rate);
|
||||
val = clkt->val;
|
||||
} else {
|
||||
val = owl_pll_calculate_mul(pll_hw, rate);
|
||||
}
|
||||
|
||||
regmap_read(common->regmap, pll_hw->reg, ®);
|
||||
|
||||
reg &= ~mul_mask(pll_hw);
|
||||
reg |= val << pll_hw->shift;
|
||||
|
||||
regmap_write(common->regmap, pll_hw->reg, reg);
|
||||
|
||||
udelay(PLL_STABILITY_WAIT_US);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops owl_pll_ops = {
|
||||
.enable = owl_pll_enable,
|
||||
.disable = owl_pll_disable,
|
||||
.is_enabled = owl_pll_is_enabled,
|
||||
.round_rate = owl_pll_round_rate,
|
||||
.recalc_rate = owl_pll_recalc_rate,
|
||||
.set_rate = owl_pll_set_rate,
|
||||
};
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL pll clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#ifndef _OWL_PLL_H_
|
||||
#define _OWL_PLL_H_
|
||||
|
||||
#include "owl-common.h"
|
||||
|
||||
/* last entry should have rate = 0 */
|
||||
struct clk_pll_table {
|
||||
unsigned int val;
|
||||
unsigned long rate;
|
||||
};
|
||||
|
||||
struct owl_pll_hw {
|
||||
u32 reg;
|
||||
u32 bfreq;
|
||||
u8 bit_idx;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 min_mul;
|
||||
u8 max_mul;
|
||||
const struct clk_pll_table *table;
|
||||
};
|
||||
|
||||
struct owl_pll {
|
||||
struct owl_pll_hw pll_hw;
|
||||
struct owl_clk_common common;
|
||||
};
|
||||
|
||||
#define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
|
||||
_width, _min_mul, _max_mul, _table) \
|
||||
{ \
|
||||
.reg = _reg, \
|
||||
.bfreq = _bfreq, \
|
||||
.bit_idx = _bit_idx, \
|
||||
.shift = _shift, \
|
||||
.width = _width, \
|
||||
.min_mul = _min_mul, \
|
||||
.max_mul = _max_mul, \
|
||||
.table = _table, \
|
||||
}
|
||||
|
||||
#define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \
|
||||
_shift, _width, _min_mul, _max_mul, _table, _flags) \
|
||||
struct owl_pll _struct = { \
|
||||
.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
|
||||
_width, _min_mul, \
|
||||
_max_mul, _table), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&owl_pll_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \
|
||||
_shift, _width, _min_mul, _max_mul, _table, _flags) \
|
||||
struct owl_pll _struct = { \
|
||||
.pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
|
||||
_width, _min_mul, \
|
||||
_max_mul, _table), \
|
||||
.common = { \
|
||||
.regmap = NULL, \
|
||||
.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
|
||||
&owl_pll_ops, \
|
||||
_flags), \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define mul_mask(m) ((1 << ((m)->width)) - 1)
|
||||
#define PLL_STABILITY_WAIT_US (50)
|
||||
|
||||
static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
|
||||
{
|
||||
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
|
||||
|
||||
return container_of(common, struct owl_pll, common);
|
||||
}
|
||||
|
||||
extern const struct clk_ops owl_pll_ops;
|
||||
|
||||
#endif /* _OWL_PLL_H_ */
|
||||
|
|
@ -0,0 +1,721 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// OWL S900 SoC clock driver
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Author: David Liu <liuwei@actions-semi.com>
|
||||
//
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "owl-common.h"
|
||||
#include "owl-composite.h"
|
||||
#include "owl-divider.h"
|
||||
#include "owl-factor.h"
|
||||
#include "owl-fixed-factor.h"
|
||||
#include "owl-gate.h"
|
||||
#include "owl-mux.h"
|
||||
#include "owl-pll.h"
|
||||
|
||||
#include <dt-bindings/clock/actions,s900-cmu.h>
|
||||
|
||||
#define CMU_COREPLL (0x0000)
|
||||
#define CMU_DEVPLL (0x0004)
|
||||
#define CMU_DDRPLL (0x0008)
|
||||
#define CMU_NANDPLL (0x000C)
|
||||
#define CMU_DISPLAYPLL (0x0010)
|
||||
#define CMU_AUDIOPLL (0x0014)
|
||||
#define CMU_TVOUTPLL (0x0018)
|
||||
#define CMU_BUSCLK (0x001C)
|
||||
#define CMU_SENSORCLK (0x0020)
|
||||
#define CMU_LCDCLK (0x0024)
|
||||
#define CMU_DSICLK (0x0028)
|
||||
#define CMU_CSICLK (0x002C)
|
||||
#define CMU_DECLK (0x0030)
|
||||
#define CMU_BISPCLK (0x0034)
|
||||
#define CMU_IMXCLK (0x0038)
|
||||
#define CMU_HDECLK (0x003C)
|
||||
#define CMU_VDECLK (0x0040)
|
||||
#define CMU_VCECLK (0x0044)
|
||||
#define CMU_NANDCCLK (0x004C)
|
||||
#define CMU_SD0CLK (0x0050)
|
||||
#define CMU_SD1CLK (0x0054)
|
||||
#define CMU_SD2CLK (0x0058)
|
||||
#define CMU_UART0CLK (0x005C)
|
||||
#define CMU_UART1CLK (0x0060)
|
||||
#define CMU_UART2CLK (0x0064)
|
||||
#define CMU_PWM0CLK (0x0070)
|
||||
#define CMU_PWM1CLK (0x0074)
|
||||
#define CMU_PWM2CLK (0x0078)
|
||||
#define CMU_PWM3CLK (0x007C)
|
||||
#define CMU_USBPLL (0x0080)
|
||||
#define CMU_ASSISTPLL (0x0084)
|
||||
#define CMU_EDPCLK (0x0088)
|
||||
#define CMU_GPU3DCLK (0x0090)
|
||||
#define CMU_CORECTL (0x009C)
|
||||
#define CMU_DEVCLKEN0 (0x00A0)
|
||||
#define CMU_DEVCLKEN1 (0x00A4)
|
||||
#define CMU_DEVRST0 (0x00A8)
|
||||
#define CMU_DEVRST1 (0x00AC)
|
||||
#define CMU_UART3CLK (0x00B0)
|
||||
#define CMU_UART4CLK (0x00B4)
|
||||
#define CMU_UART5CLK (0x00B8)
|
||||
#define CMU_UART6CLK (0x00BC)
|
||||
#define CMU_TLSCLK (0x00C0)
|
||||
#define CMU_SD3CLK (0x00C4)
|
||||
#define CMU_PWM4CLK (0x00C8)
|
||||
#define CMU_PWM5CLK (0x00CC)
|
||||
|
||||
static struct clk_pll_table clk_audio_pll_table[] = {
|
||||
{ 0, 45158400 }, { 1, 49152000 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_pll_table clk_edp_pll_table[] = {
|
||||
{ 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
/* pll clocks */
|
||||
static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
|
||||
static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
|
||||
|
||||
static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
|
||||
static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
|
||||
static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
|
||||
static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
|
||||
static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
|
||||
static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
|
||||
static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
|
||||
static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
|
||||
static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
|
||||
static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
|
||||
static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
|
||||
static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
|
||||
static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
|
||||
static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
|
||||
static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
|
||||
static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
|
||||
static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
|
||||
static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
|
||||
|
||||
/* mux clocks */
|
||||
static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
|
||||
static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
|
||||
static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
|
||||
|
||||
static struct clk_div_table nand_div_table[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
|
||||
{ 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
|
||||
{ 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_div_table apb_div_table[] = {
|
||||
{ 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_div_table eth_mac_div_table[] = {
|
||||
{ 0, 2 }, { 1, 4 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_div_table rmii_ref_div_table[] = {
|
||||
{ 0, 4 }, { 1, 10 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_div_table usb3_mac_div_table[] = {
|
||||
{ 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 0, 8 },
|
||||
};
|
||||
|
||||
static struct clk_div_table i2s_div_table[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
|
||||
{ 8, 24 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_div_table hdmia_div_table[] = {
|
||||
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
|
||||
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
|
||||
{ 8, 24 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
/* divider clocks */
|
||||
static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
|
||||
static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
|
||||
static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
|
||||
static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
|
||||
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
|
||||
|
||||
static struct clk_factor_table sd_factor_table[] = {
|
||||
/* bit0 ~ 4 */
|
||||
{ 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
|
||||
{ 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
|
||||
{ 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
|
||||
{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
|
||||
{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
|
||||
{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
|
||||
{ 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
|
||||
{ 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
|
||||
|
||||
/* bit8: /128 */
|
||||
{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
|
||||
{ 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
|
||||
{ 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
|
||||
{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
|
||||
{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
|
||||
{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
|
||||
{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
|
||||
{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
|
||||
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_factor_table dmm_factor_table[] = {
|
||||
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
|
||||
{ 4, 1, 4 },
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_factor_table noc_factor_table[] = {
|
||||
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk_factor_table bisp_factor_table[] = {
|
||||
{ 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
|
||||
{ 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
|
||||
{ 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* factor clocks */
|
||||
static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
|
||||
static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
|
||||
static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
|
||||
static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
|
||||
|
||||
/* gate clocks */
|
||||
static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
|
||||
static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
|
||||
static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
|
||||
static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
|
||||
static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
|
||||
static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
|
||||
static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
|
||||
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
|
||||
static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
|
||||
|
||||
/* composite clocks */
|
||||
static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
|
||||
OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_CSICLK, 4, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
|
||||
OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_CSICLK, 20, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
|
||||
OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_DECLK, 12, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_BUSCLK, 10, 2),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
|
||||
OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_EDPCLK, 19, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
|
||||
OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
|
||||
OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
|
||||
OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
|
||||
OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
|
||||
OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
|
||||
OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
|
||||
OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
|
||||
OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_HDECLK, 4, 2),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
|
||||
OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
|
||||
OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
|
||||
1, 5, 0);
|
||||
|
||||
static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
|
||||
OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
|
||||
OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_IMXCLK, 4, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
|
||||
OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_LCDCLK, 12, 2),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
|
||||
OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
|
||||
OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
|
||||
OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
|
||||
0);
|
||||
/*
|
||||
* pwm2 may be for backlight, do not gate it
|
||||
* even it is "unused", because it may be
|
||||
* enabled at boot stage, and in kernel, driver
|
||||
* has no effective method to know the real status,
|
||||
* so, the best way is keeping it as what it was.
|
||||
*/
|
||||
static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
|
||||
OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
|
||||
OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_SD1CLK, 9, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
|
||||
OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_SD2CLK, 9, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
|
||||
OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_SD3CLK, 9, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
|
||||
OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
|
||||
OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
|
||||
"hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
|
||||
OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
|
||||
"hosc",
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
|
||||
OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
|
||||
0);
|
||||
|
||||
static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART1CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
|
||||
OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
|
||||
CLK_IGNORE_UNUSED);
|
||||
|
||||
static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_VCECLK, 4, 2),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
|
||||
OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
|
||||
OWL_MUX_HW(CMU_VDECLK, 4, 2),
|
||||
OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
|
||||
OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
|
||||
0);
|
||||
|
||||
static struct owl_clk_common *s900_clks[] = {
|
||||
&core_pll_clk.common,
|
||||
&dev_pll_clk.common,
|
||||
&ddr_pll_clk.common,
|
||||
&nand_pll_clk.common,
|
||||
&display_pll_clk.common,
|
||||
&assist_pll_clk.common,
|
||||
&audio_pll_clk.common,
|
||||
&edp_pll_clk.common,
|
||||
&cpu_clk.common,
|
||||
&dev_clk.common,
|
||||
&noc_clk_mux.common,
|
||||
&noc_clk_div.common,
|
||||
&ahb_clk.common,
|
||||
&apb_clk.common,
|
||||
&usb3_mac_clk.common,
|
||||
&rmii_ref_clk.common,
|
||||
&noc_clk.common,
|
||||
&de_clk1.common,
|
||||
&de_clk2.common,
|
||||
&de_clk3.common,
|
||||
&gpio_clk.common,
|
||||
&gpu_clk.common,
|
||||
&dmac_clk.common,
|
||||
&timer_clk.common,
|
||||
&dsi_clk.common,
|
||||
&ddr0_clk.common,
|
||||
&ddr1_clk.common,
|
||||
&usb3_480mpll0_clk.common,
|
||||
&usb3_480mphy0_clk.common,
|
||||
&usb3_5gphy_clk.common,
|
||||
&usb3_cce_clk.common,
|
||||
&edp24M_clk.common,
|
||||
&edp_link_clk.common,
|
||||
&usbh0_pllen_clk.common,
|
||||
&usbh0_phy_clk.common,
|
||||
&usbh0_cce_clk.common,
|
||||
&usbh1_pllen_clk.common,
|
||||
&usbh1_phy_clk.common,
|
||||
&usbh1_cce_clk.common,
|
||||
&i2c0_clk.common,
|
||||
&i2c1_clk.common,
|
||||
&i2c2_clk.common,
|
||||
&i2c3_clk.common,
|
||||
&i2c4_clk.common,
|
||||
&i2c5_clk.common,
|
||||
&spi0_clk.common,
|
||||
&spi1_clk.common,
|
||||
&spi2_clk.common,
|
||||
&spi3_clk.common,
|
||||
&bisp_clk.common,
|
||||
&csi0_clk.common,
|
||||
&csi1_clk.common,
|
||||
&de_clk.common,
|
||||
&dmm_clk.common,
|
||||
&edp_clk.common,
|
||||
ð_mac_clk.common,
|
||||
&gpu_core_clk.common,
|
||||
&gpu_mem_clk.common,
|
||||
&gpu_sys_clk.common,
|
||||
&hde_clk.common,
|
||||
&hdmia_clk.common,
|
||||
&i2srx_clk.common,
|
||||
&i2stx_clk.common,
|
||||
&imx_clk.common,
|
||||
&lcd_clk.common,
|
||||
&nand0_clk.common,
|
||||
&nand1_clk.common,
|
||||
&pwm0_clk.common,
|
||||
&pwm1_clk.common,
|
||||
&pwm2_clk.common,
|
||||
&pwm3_clk.common,
|
||||
&pwm4_clk.common,
|
||||
&pwm5_clk.common,
|
||||
&sd0_clk.common,
|
||||
&sd1_clk.common,
|
||||
&sd2_clk.common,
|
||||
&sd3_clk.common,
|
||||
&sensor_clk.common,
|
||||
&speed_sensor_clk.common,
|
||||
&thermal_sensor_clk.common,
|
||||
&uart0_clk.common,
|
||||
&uart1_clk.common,
|
||||
&uart2_clk.common,
|
||||
&uart3_clk.common,
|
||||
&uart4_clk.common,
|
||||
&uart5_clk.common,
|
||||
&uart6_clk.common,
|
||||
&vce_clk.common,
|
||||
&vde_clk.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data s900_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_CORE_PLL] = &core_pll_clk.common.hw,
|
||||
[CLK_DEV_PLL] = &dev_pll_clk.common.hw,
|
||||
[CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
|
||||
[CLK_NAND_PLL] = &nand_pll_clk.common.hw,
|
||||
[CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
|
||||
[CLK_ASSIST_PLL] = &assist_pll_clk.common.hw,
|
||||
[CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
|
||||
[CLK_EDP_PLL] = &edp_pll_clk.common.hw,
|
||||
[CLK_CPU] = &cpu_clk.common.hw,
|
||||
[CLK_DEV] = &dev_clk.common.hw,
|
||||
[CLK_NOC_MUX] = &noc_clk_mux.common.hw,
|
||||
[CLK_NOC_DIV] = &noc_clk_div.common.hw,
|
||||
[CLK_AHB] = &ahb_clk.common.hw,
|
||||
[CLK_APB] = &apb_clk.common.hw,
|
||||
[CLK_USB3_MAC] = &usb3_mac_clk.common.hw,
|
||||
[CLK_RMII_REF] = &rmii_ref_clk.common.hw,
|
||||
[CLK_NOC] = &noc_clk.common.hw,
|
||||
[CLK_DE1] = &de_clk1.common.hw,
|
||||
[CLK_DE2] = &de_clk2.common.hw,
|
||||
[CLK_DE3] = &de_clk3.common.hw,
|
||||
[CLK_GPIO] = &gpio_clk.common.hw,
|
||||
[CLK_GPU] = &gpu_clk.common.hw,
|
||||
[CLK_DMAC] = &dmac_clk.common.hw,
|
||||
[CLK_TIMER] = &timer_clk.common.hw,
|
||||
[CLK_DSI] = &dsi_clk.common.hw,
|
||||
[CLK_DDR0] = &ddr0_clk.common.hw,
|
||||
[CLK_DDR1] = &ddr1_clk.common.hw,
|
||||
[CLK_USB3_480MPLL0] = &usb3_480mpll0_clk.common.hw,
|
||||
[CLK_USB3_480MPHY0] = &usb3_480mphy0_clk.common.hw,
|
||||
[CLK_USB3_5GPHY] = &usb3_5gphy_clk.common.hw,
|
||||
[CLK_USB3_CCE] = &usb3_cce_clk.common.hw,
|
||||
[CLK_24M_EDP] = &edp24M_clk.common.hw,
|
||||
[CLK_EDP_LINK] = &edp_link_clk.common.hw,
|
||||
[CLK_USB2H0_PLLEN] = &usbh0_pllen_clk.common.hw,
|
||||
[CLK_USB2H0_PHY] = &usbh0_phy_clk.common.hw,
|
||||
[CLK_USB2H0_CCE] = &usbh0_cce_clk.common.hw,
|
||||
[CLK_USB2H1_PLLEN] = &usbh1_pllen_clk.common.hw,
|
||||
[CLK_USB2H1_PHY] = &usbh1_phy_clk.common.hw,
|
||||
[CLK_USB2H1_CCE] = &usbh1_cce_clk.common.hw,
|
||||
[CLK_I2C0] = &i2c0_clk.common.hw,
|
||||
[CLK_I2C1] = &i2c1_clk.common.hw,
|
||||
[CLK_I2C2] = &i2c2_clk.common.hw,
|
||||
[CLK_I2C3] = &i2c3_clk.common.hw,
|
||||
[CLK_I2C4] = &i2c4_clk.common.hw,
|
||||
[CLK_I2C5] = &i2c5_clk.common.hw,
|
||||
[CLK_SPI0] = &spi0_clk.common.hw,
|
||||
[CLK_SPI1] = &spi1_clk.common.hw,
|
||||
[CLK_SPI2] = &spi2_clk.common.hw,
|
||||
[CLK_SPI3] = &spi3_clk.common.hw,
|
||||
[CLK_BISP] = &bisp_clk.common.hw,
|
||||
[CLK_CSI0] = &csi0_clk.common.hw,
|
||||
[CLK_CSI1] = &csi1_clk.common.hw,
|
||||
[CLK_DE0] = &de_clk.common.hw,
|
||||
[CLK_DMM] = &dmm_clk.common.hw,
|
||||
[CLK_EDP] = &edp_clk.common.hw,
|
||||
[CLK_ETH_MAC] = ð_mac_clk.common.hw,
|
||||
[CLK_GPU_CORE] = &gpu_core_clk.common.hw,
|
||||
[CLK_GPU_MEM] = &gpu_mem_clk.common.hw,
|
||||
[CLK_GPU_SYS] = &gpu_sys_clk.common.hw,
|
||||
[CLK_HDE] = &hde_clk.common.hw,
|
||||
[CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
|
||||
[CLK_I2SRX] = &i2srx_clk.common.hw,
|
||||
[CLK_I2STX] = &i2stx_clk.common.hw,
|
||||
[CLK_IMX] = &imx_clk.common.hw,
|
||||
[CLK_LCD] = &lcd_clk.common.hw,
|
||||
[CLK_NAND0] = &nand0_clk.common.hw,
|
||||
[CLK_NAND1] = &nand1_clk.common.hw,
|
||||
[CLK_PWM0] = &pwm0_clk.common.hw,
|
||||
[CLK_PWM1] = &pwm1_clk.common.hw,
|
||||
[CLK_PWM2] = &pwm2_clk.common.hw,
|
||||
[CLK_PWM3] = &pwm3_clk.common.hw,
|
||||
[CLK_PWM4] = &pwm4_clk.common.hw,
|
||||
[CLK_PWM5] = &pwm5_clk.common.hw,
|
||||
[CLK_SD0] = &sd0_clk.common.hw,
|
||||
[CLK_SD1] = &sd1_clk.common.hw,
|
||||
[CLK_SD2] = &sd2_clk.common.hw,
|
||||
[CLK_SD3] = &sd3_clk.common.hw,
|
||||
[CLK_SENSOR] = &sensor_clk.common.hw,
|
||||
[CLK_SPEED_SENSOR] = &speed_sensor_clk.common.hw,
|
||||
[CLK_THERMAL_SENSOR] = &thermal_sensor_clk.common.hw,
|
||||
[CLK_UART0] = &uart0_clk.common.hw,
|
||||
[CLK_UART1] = &uart1_clk.common.hw,
|
||||
[CLK_UART2] = &uart2_clk.common.hw,
|
||||
[CLK_UART3] = &uart3_clk.common.hw,
|
||||
[CLK_UART4] = &uart4_clk.common.hw,
|
||||
[CLK_UART5] = &uart5_clk.common.hw,
|
||||
[CLK_UART6] = &uart6_clk.common.hw,
|
||||
[CLK_VCE] = &vce_clk.common.hw,
|
||||
[CLK_VDE] = &vde_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NR_CLKS,
|
||||
};
|
||||
|
||||
static const struct owl_clk_desc s900_clk_desc = {
|
||||
.clks = s900_clks,
|
||||
.num_clks = ARRAY_SIZE(s900_clks),
|
||||
|
||||
.hw_clks = &s900_hw_clks,
|
||||
};
|
||||
|
||||
static int s900_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct owl_clk_desc *desc;
|
||||
|
||||
desc = &s900_clk_desc;
|
||||
owl_clk_regmap_init(pdev, desc);
|
||||
|
||||
return owl_clk_probe(&pdev->dev, desc->hw_clks);
|
||||
}
|
||||
|
||||
static const struct of_device_id s900_clk_of_match[] = {
|
||||
{ .compatible = "actions,s900-cmu", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver s900_clk_driver = {
|
||||
.probe = s900_clk_probe,
|
||||
.driver = {
|
||||
.name = "s900-cmu",
|
||||
.of_match_table = s900_clk_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init s900_clk_init(void)
|
||||
{
|
||||
return platform_driver_register(&s900_clk_driver);
|
||||
}
|
||||
core_initcall(s900_clk_init);
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Device Tree binding constants for Actions Semi S900 Clock Management Unit
|
||||
//
|
||||
// Copyright (c) 2014 Actions Semi Inc.
|
||||
// Copyright (c) 2018 Linaro Ltd.
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
|
||||
#define __DT_BINDINGS_CLOCK_S900_CMU_H
|
||||
|
||||
#define CLK_NONE 0
|
||||
|
||||
/* fixed rate clocks */
|
||||
#define CLK_LOSC 1
|
||||
#define CLK_HOSC 2
|
||||
|
||||
/* pll clocks */
|
||||
#define CLK_CORE_PLL 3
|
||||
#define CLK_DEV_PLL 4
|
||||
#define CLK_DDR_PLL 5
|
||||
#define CLK_NAND_PLL 6
|
||||
#define CLK_DISPLAY_PLL 7
|
||||
#define CLK_DSI_PLL 8
|
||||
#define CLK_ASSIST_PLL 9
|
||||
#define CLK_AUDIO_PLL 10
|
||||
|
||||
/* system clock */
|
||||
#define CLK_CPU 15
|
||||
#define CLK_DEV 16
|
||||
#define CLK_NOC 17
|
||||
#define CLK_NOC_MUX 18
|
||||
#define CLK_NOC_DIV 19
|
||||
#define CLK_AHB 20
|
||||
#define CLK_APB 21
|
||||
#define CLK_DMAC 22
|
||||
|
||||
/* peripheral device clock */
|
||||
#define CLK_GPIO 23
|
||||
|
||||
#define CLK_BISP 24
|
||||
#define CLK_CSI0 25
|
||||
#define CLK_CSI1 26
|
||||
|
||||
#define CLK_DE0 27
|
||||
#define CLK_DE1 28
|
||||
#define CLK_DE2 29
|
||||
#define CLK_DE3 30
|
||||
#define CLK_DSI 32
|
||||
|
||||
#define CLK_GPU 33
|
||||
#define CLK_GPU_CORE 34
|
||||
#define CLK_GPU_MEM 35
|
||||
#define CLK_GPU_SYS 36
|
||||
|
||||
#define CLK_HDE 37
|
||||
#define CLK_I2C0 38
|
||||
#define CLK_I2C1 39
|
||||
#define CLK_I2C2 40
|
||||
#define CLK_I2C3 41
|
||||
#define CLK_I2C4 42
|
||||
#define CLK_I2C5 43
|
||||
#define CLK_I2SRX 44
|
||||
#define CLK_I2STX 45
|
||||
#define CLK_IMX 46
|
||||
#define CLK_LCD 47
|
||||
#define CLK_NAND0 48
|
||||
#define CLK_NAND1 49
|
||||
#define CLK_PWM0 50
|
||||
#define CLK_PWM1 51
|
||||
#define CLK_PWM2 52
|
||||
#define CLK_PWM3 53
|
||||
#define CLK_PWM4 54
|
||||
#define CLK_PWM5 55
|
||||
#define CLK_SD0 56
|
||||
#define CLK_SD1 57
|
||||
#define CLK_SD2 58
|
||||
#define CLK_SD3 59
|
||||
#define CLK_SENSOR 60
|
||||
#define CLK_SPEED_SENSOR 61
|
||||
#define CLK_SPI0 62
|
||||
#define CLK_SPI1 63
|
||||
#define CLK_SPI2 64
|
||||
#define CLK_SPI3 65
|
||||
#define CLK_THERMAL_SENSOR 66
|
||||
#define CLK_UART0 67
|
||||
#define CLK_UART1 68
|
||||
#define CLK_UART2 69
|
||||
#define CLK_UART3 70
|
||||
#define CLK_UART4 71
|
||||
#define CLK_UART5 72
|
||||
#define CLK_UART6 73
|
||||
#define CLK_VCE 74
|
||||
#define CLK_VDE 75
|
||||
|
||||
#define CLK_USB3_480MPLL0 76
|
||||
#define CLK_USB3_480MPHY0 77
|
||||
#define CLK_USB3_5GPHY 78
|
||||
#define CLK_USB3_CCE 79
|
||||
#define CLK_USB3_MAC 80
|
||||
|
||||
#define CLK_TIMER 83
|
||||
|
||||
#define CLK_HDMI_AUDIO 84
|
||||
|
||||
#define CLK_24M 85
|
||||
|
||||
#define CLK_EDP 86
|
||||
|
||||
#define CLK_24M_EDP 87
|
||||
#define CLK_EDP_PLL 88
|
||||
#define CLK_EDP_LINK 89
|
||||
|
||||
#define CLK_USB2H0_PLLEN 90
|
||||
#define CLK_USB2H0_PHY 91
|
||||
#define CLK_USB2H0_CCE 92
|
||||
#define CLK_USB2H1_PLLEN 93
|
||||
#define CLK_USB2H1_PHY 94
|
||||
#define CLK_USB2H1_CCE 95
|
||||
|
||||
#define CLK_DDR0 96
|
||||
#define CLK_DDR1 97
|
||||
#define CLK_DMM 98
|
||||
|
||||
#define CLK_ETH_MAC 99
|
||||
#define CLK_RMII_REF 100
|
||||
|
||||
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */
|
||||
Loading…
Reference in New Issue