Merge branch 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-cleanups-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Remove trailing spaces in messages x86, mtrr: Remove unused mtrr/state.c x86, trivial: Fix grammo in tsc comment about Geode TSC reliability
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commit
43a834d86c
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@ -1,3 +1,3 @@
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obj-y := main.o if.o generic.o state.o cleanup.o
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obj-y := main.o if.o generic.o cleanup.o
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obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o
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@ -1,94 +0,0 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <asm/processor-cyrix.h>
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#include <asm/processor-flags.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "mtrr.h"
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/* Put the processor into a state where MTRRs can be safely set */
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void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
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{
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unsigned int cr0;
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/* Disable interrupts locally */
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local_irq_save(ctxt->flags);
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if (use_intel() || is_cpu(CYRIX)) {
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if (cpu_has_pge) {
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ctxt->cr4val = read_cr4();
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write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
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}
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/*
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* Disable and flush caches. Note that wbinvd flushes the TLBs
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* as a side-effect
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*/
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cr0 = read_cr0() | X86_CR0_CD;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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if (use_intel()) {
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/* Save MTRR state */
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rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
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} else {
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/*
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* Cyrix ARRs -
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* everything else were excluded at the top
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*/
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ctxt->ccr3 = getCx86(CX86_CCR3);
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}
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}
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}
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void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
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{
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if (use_intel()) {
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/* Disable MTRRs, and set the default type to uncached */
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mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
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ctxt->deftype_hi);
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} else {
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if (is_cpu(CYRIX)) {
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/* Cyrix ARRs - everything else were excluded at the top */
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setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
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}
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}
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}
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/* Restore the processor after a set_mtrr_prepare */
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void set_mtrr_done(struct set_mtrr_context *ctxt)
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{
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if (use_intel() || is_cpu(CYRIX)) {
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/* Flush caches and TLBs */
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wbinvd();
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/* Restore MTRRdefType */
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if (use_intel()) {
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/* Intel (P6) standard MTRRs */
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mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo,
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ctxt->deftype_hi);
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} else {
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/*
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* Cyrix ARRs -
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* everything else was excluded at the top
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*/
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setCx86(CX86_CCR3, ctxt->ccr3);
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}
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/* Enable caches */
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write_cr0(read_cr0() & 0xbfffffff);
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/* Restore value of CR4 */
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if (cpu_has_pge)
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write_cr4(ctxt->cr4val);
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}
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/* Re-enable interrupts locally (if enabled previously) */
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local_irq_restore(ctxt->flags);
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}
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@ -806,7 +806,7 @@ static void __init check_system_tsc_reliable(void)
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unsigned long res_low, res_high;
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rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
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/* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */
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/* Geode_LX - the OLPC CPU has a very reliable TSC */
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if (res_low & RTSC_SUSP)
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tsc_clocksource_reliable = 1;
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#endif
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