ath10k: move ath10k_hw_params definition to hw.h
This is to prepare for rx descriptor abstraction where we'll be dereferencing ath10k_hw_params member in hw.h. Moreover hw.h looks more suitable to house ath10k_hw_params definition than core.h Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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@ -736,58 +736,7 @@ struct ath10k {
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struct ath10k_htc htc;
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struct ath10k_htt htt;
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struct ath10k_hw_params {
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u32 id;
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u16 dev_id;
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const char *name;
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u32 patch_load_addr;
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int uart_pin;
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u32 otp_exe_param;
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/* Type of hw cycle counter wraparound logic, for more info
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* refer enum ath10k_hw_cc_wraparound_type.
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*/
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enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
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/* Some of chip expects fragment descriptor to be continuous
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* memory for any TX operation. Set continuous_frag_desc flag
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* for the hardware which have such requirement.
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*/
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bool continuous_frag_desc;
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/* CCK hardware rate table mapping for the newer chipsets
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* like QCA99X0, QCA4019 got revised. The CCK h/w rate values
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* are in a proper order with respect to the rate/preamble
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*/
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bool cck_rate_map_rev2;
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u32 channel_counters_freq_hz;
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/* Mgmt tx descriptors threshold for limiting probe response
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* frames.
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*/
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u32 max_probe_resp_desc_thres;
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/* The padding bytes's location is different on various chips */
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enum ath10k_hw_4addr_pad hw_4addr_pad;
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u32 tx_chain_mask;
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u32 rx_chain_mask;
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u32 max_spatial_stream;
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u32 cal_data_len;
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struct ath10k_hw_params_fw {
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const char *dir;
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const char *board;
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size_t board_size;
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size_t board_ext_size;
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} fw;
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/* qca99x0 family chips deliver broadcast/multicast management
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* frames encrypted and expect software do decryption.
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*/
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bool sw_decrypt_mcast_mgmt;
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} hw_params;
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struct ath10k_hw_params hw_params;
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/* contains the firmware images used with ATH10K_FIRMWARE_MODE_NORMAL */
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struct ath10k_fw_components normal_mode_fw;
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@ -363,6 +363,59 @@ enum ath10k_hw_cc_wraparound_type {
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ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
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};
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struct ath10k_hw_params {
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u32 id;
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u16 dev_id;
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const char *name;
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u32 patch_load_addr;
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int uart_pin;
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u32 otp_exe_param;
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/* Type of hw cycle counter wraparound logic, for more info
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* refer enum ath10k_hw_cc_wraparound_type.
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*/
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enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
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/* Some of chip expects fragment descriptor to be continuous
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* memory for any TX operation. Set continuous_frag_desc flag
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* for the hardware which have such requirement.
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*/
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bool continuous_frag_desc;
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/* CCK hardware rate table mapping for the newer chipsets
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* like QCA99X0, QCA4019 got revised. The CCK h/w rate values
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* are in a proper order with respect to the rate/preamble
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*/
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bool cck_rate_map_rev2;
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u32 channel_counters_freq_hz;
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/* Mgmt tx descriptors threshold for limiting probe response
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* frames.
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*/
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u32 max_probe_resp_desc_thres;
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/* The padding bytes's location is different on various chips */
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enum ath10k_hw_4addr_pad hw_4addr_pad;
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u32 tx_chain_mask;
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u32 rx_chain_mask;
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u32 max_spatial_stream;
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u32 cal_data_len;
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struct ath10k_hw_params_fw {
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const char *dir;
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const char *board;
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size_t board_size;
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size_t board_ext_size;
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} fw;
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/* qca99x0 family chips deliver broadcast/multicast management
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* frames encrypted and expect software do decryption.
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*/
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bool sw_decrypt_mcast_mgmt;
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};
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/* Target specific defines for MAIN firmware */
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#define TARGET_NUM_VDEVS 8
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#define TARGET_NUM_PEER_AST 2
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