amd-xgbe: Perform priority-based hardware FIFO allocation
Allocate the FIFO across the hardware Rx queues based on the priority of the queues. Giving more FIFO resources to queues with a higher priority. If PFC is active but not enabled for a queue, then less resources can allocated to the queue. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Lendacky, Thomas
David S. Miller
parent
586e3cfb26
commit
43e0dcf708
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@ -123,6 +123,11 @@
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#include "xgbe.h"
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#include "xgbe-common.h"
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static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata)
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{
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return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
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}
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static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
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unsigned int usec)
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{
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@ -491,6 +496,27 @@ static void xgbe_config_rss(struct xgbe_prv_data *pdata)
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"error configuring RSS, RSS disabled\n");
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}
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static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata,
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unsigned int queue)
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{
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unsigned int prio, tc;
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for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
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/* Does this queue handle the priority? */
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if (pdata->prio2q_map[prio] != queue)
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continue;
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/* Get the Traffic Class for this priority */
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tc = pdata->ets->prio_tc[prio];
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/* Check if PFC is enabled for this traffic class */
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if (pdata->pfc->pfc_en & (1 << tc))
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return true;
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}
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return false;
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}
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static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
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{
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unsigned int max_q_count, q_count;
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@ -528,27 +554,14 @@ static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
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for (i = 0; i < pdata->rx_q_count; i++) {
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unsigned int ehfc = 0;
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if (pfc && ets) {
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unsigned int prio;
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for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
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unsigned int tc;
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/* Does this queue handle the priority? */
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if (pdata->prio2q_map[prio] != i)
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continue;
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/* Get the Traffic Class for this priority */
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tc = ets->prio_tc[prio];
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/* Check if flow control should be enabled */
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if (pfc->pfc_en & (1 << tc)) {
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if (pdata->rx_rfd[i]) {
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/* Flow control thresholds are established */
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if (pfc && ets) {
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if (xgbe_is_pfc_queue(pdata, i))
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ehfc = 1;
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break;
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}
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} else {
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ehfc = 1;
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}
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} else {
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ehfc = 1;
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}
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc);
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@ -1327,106 +1340,6 @@ static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
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return 0;
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}
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static void xgbe_config_tc(struct xgbe_prv_data *pdata)
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{
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unsigned int offset, queue, prio;
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u8 i;
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netdev_reset_tc(pdata->netdev);
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if (!pdata->num_tcs)
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return;
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netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
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for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
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while ((queue < pdata->tx_q_count) &&
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(pdata->q2tc_map[queue] == i))
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queue++;
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netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
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i, offset, queue - 1);
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netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
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offset = queue;
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}
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if (!pdata->ets)
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return;
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for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
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netdev_set_prio_tc_map(pdata->netdev, prio,
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pdata->ets->prio_tc[prio]);
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}
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static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
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{
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struct ieee_ets *ets = pdata->ets;
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unsigned int total_weight, min_weight, weight;
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unsigned int mask, reg, reg_val;
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unsigned int i, prio;
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if (!ets)
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return;
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/* Set Tx to deficit weighted round robin scheduling algorithm (when
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* traffic class is using ETS algorithm)
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*/
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XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
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/* Set Traffic Class algorithms */
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total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
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min_weight = total_weight / 100;
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if (!min_weight)
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min_weight = 1;
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for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
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/* Map the priorities to the traffic class */
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mask = 0;
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for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
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if (ets->prio_tc[prio] == i)
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mask |= (1 << prio);
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}
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mask &= 0xff;
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netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
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i, mask);
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reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG));
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reg_val = XGMAC_IOREAD(pdata, reg);
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reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));
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reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));
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XGMAC_IOWRITE(pdata, reg, reg_val);
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/* Set the traffic class algorithm */
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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netif_dbg(pdata, drv, pdata->netdev,
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"TC%u using SP\n", i);
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
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MTL_TSA_SP);
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break;
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case IEEE_8021QAZ_TSA_ETS:
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weight = total_weight * ets->tc_tx_bw[i] / 100;
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weight = clamp(weight, min_weight, total_weight);
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netif_dbg(pdata, drv, pdata->netdev,
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"TC%u using DWRR (weight %u)\n", i, weight);
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
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MTL_TSA_ETS);
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
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weight);
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break;
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}
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}
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xgbe_config_tc(pdata);
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}
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static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
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{
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xgbe_config_flow_control(pdata);
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}
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static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
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struct xgbe_ring *ring)
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{
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@ -2000,6 +1913,96 @@ static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
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XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
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}
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static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata,
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unsigned int queue,
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unsigned int q_fifo_size)
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{
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unsigned int frame_fifo_size;
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unsigned int rfa, rfd;
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frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata));
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if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) {
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/* PFC is active for this queue */
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rfa = pdata->pfc_rfa;
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rfd = rfa + frame_fifo_size;
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if (rfd > XGMAC_FLOW_CONTROL_MAX)
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rfd = XGMAC_FLOW_CONTROL_MAX;
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if (rfa >= XGMAC_FLOW_CONTROL_MAX)
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rfa = XGMAC_FLOW_CONTROL_MAX - XGMAC_FLOW_CONTROL_UNIT;
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} else {
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/* This path deals with just maximum frame sizes which are
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* limited to a jumbo frame of 9,000 (plus headers, etc.)
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* so we can never exceed the maximum allowable RFA/RFD
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* values.
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*/
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if (q_fifo_size <= 2048) {
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/* rx_rfd to zero to signal no flow control */
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pdata->rx_rfa[queue] = 0;
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pdata->rx_rfd[queue] = 0;
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return;
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}
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if (q_fifo_size <= 4096) {
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/* Between 2048 and 4096 */
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pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */
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pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */
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return;
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}
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if (q_fifo_size <= frame_fifo_size) {
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/* Between 4096 and max-frame */
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pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */
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pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */
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return;
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}
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if (q_fifo_size <= (frame_fifo_size * 3)) {
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/* Between max-frame and 3 max-frames,
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* trigger if we get just over a frame of data and
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* resume when we have just under half a frame left.
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*/
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rfa = q_fifo_size - frame_fifo_size;
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rfd = rfa + (frame_fifo_size / 2);
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} else {
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/* Above 3 max-frames - trigger when just over
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* 2 frames of space available
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*/
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rfa = frame_fifo_size * 2;
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rfa += XGMAC_FLOW_CONTROL_UNIT;
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rfd = rfa + frame_fifo_size;
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}
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}
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pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa);
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pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd);
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}
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static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata,
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unsigned int *fifo)
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{
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unsigned int q_fifo_size;
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unsigned int i;
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for (i = 0; i < pdata->rx_q_count; i++) {
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q_fifo_size = (fifo[i] + 1) * XGMAC_FIFO_UNIT;
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xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size);
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}
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}
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static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
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{
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unsigned int i;
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for (i = 0; i < pdata->rx_q_count; i++) {
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA,
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pdata->rx_rfa[i]);
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XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD,
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pdata->rx_rfd[i]);
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}
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}
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static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata)
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{
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unsigned int fifo_size;
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@ -2032,18 +2035,158 @@ static void xgbe_calculate_equal_fifo(unsigned int fifo_size,
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q_fifo_size = fifo_size / queue_count;
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/* Each increment in the queue fifo size represents 256 bytes of
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* fifo, with 0 representing 256 bytes. Distribute the fifo equally
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* between the queues.
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/* Calculate the fifo setting by dividing the queue's fifo size
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* by the fifo allocation increment (with 0 representing the
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* base allocation increment so decrement the result by 1).
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*/
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p_fifo = q_fifo_size / 256;
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p_fifo = q_fifo_size / XGMAC_FIFO_UNIT;
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if (p_fifo)
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p_fifo--;
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/* Distribute the fifo equally amongst the queues */
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for (i = 0; i < queue_count; i++)
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fifo[i] = p_fifo;
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}
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static unsigned int xgbe_set_nonprio_fifos(unsigned int fifo_size,
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unsigned int queue_count,
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unsigned int *fifo)
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{
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unsigned int i;
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BUILD_BUG_ON_NOT_POWER_OF_2(XGMAC_FIFO_MIN_ALLOC);
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if (queue_count <= IEEE_8021QAZ_MAX_TCS)
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return fifo_size;
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/* Rx queues 9 and up are for specialized packets,
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* such as PTP or DCB control packets, etc. and
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* don't require a large fifo
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*/
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for (i = IEEE_8021QAZ_MAX_TCS; i < queue_count; i++) {
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fifo[i] = (XGMAC_FIFO_MIN_ALLOC / XGMAC_FIFO_UNIT) - 1;
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fifo_size -= XGMAC_FIFO_MIN_ALLOC;
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}
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return fifo_size;
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}
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static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata)
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{
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unsigned int delay;
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/* If a delay has been provided, use that */
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if (pdata->pfc->delay)
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return pdata->pfc->delay / 8;
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/* Allow for two maximum size frames */
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delay = xgbe_get_max_frame(pdata);
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delay += XGMAC_ETH_PREAMBLE;
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delay *= 2;
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/* Allow for PFC frame */
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delay += XGMAC_PFC_DATA_LEN;
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delay += ETH_HLEN + ETH_FCS_LEN;
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delay += XGMAC_ETH_PREAMBLE;
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/* Allow for miscellaneous delays (LPI exit, cable, etc.) */
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delay += XGMAC_PFC_DELAYS;
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return delay;
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}
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static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata)
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{
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unsigned int count, prio_queues;
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unsigned int i;
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if (!pdata->pfc->pfc_en)
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return 0;
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count = 0;
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prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
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for (i = 0; i < prio_queues; i++) {
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if (!xgbe_is_pfc_queue(pdata, i))
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continue;
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pdata->pfcq[i] = 1;
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count++;
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}
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return count;
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}
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static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata,
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unsigned int fifo_size,
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unsigned int *fifo)
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{
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unsigned int q_fifo_size, rem_fifo, addn_fifo;
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unsigned int prio_queues;
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unsigned int pfc_count;
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unsigned int i;
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q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata));
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prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
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pfc_count = xgbe_get_pfc_queues(pdata);
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if (!pfc_count || ((q_fifo_size * prio_queues) > fifo_size)) {
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/* No traffic classes with PFC enabled or can't do lossless */
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xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
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return;
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}
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/* Calculate how much fifo we have to play with */
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rem_fifo = fifo_size - (q_fifo_size * prio_queues);
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/* Calculate how much more than base fifo PFC needs, which also
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* becomes the threshold activation point (RFA)
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*/
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pdata->pfc_rfa = xgbe_get_pfc_delay(pdata);
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pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa);
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if (pdata->pfc_rfa > q_fifo_size) {
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addn_fifo = pdata->pfc_rfa - q_fifo_size;
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addn_fifo = XGMAC_FIFO_ALIGN(addn_fifo);
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} else {
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addn_fifo = 0;
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}
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/* Calculate DCB fifo settings:
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* - distribute remaining fifo between the VLAN priority
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* queues based on traffic class PFC enablement and overall
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* priority (0 is lowest priority, so start at highest)
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*/
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i = prio_queues;
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while (i > 0) {
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i--;
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fifo[i] = (q_fifo_size / XGMAC_FIFO_UNIT) - 1;
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if (!pdata->pfcq[i] || !addn_fifo)
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continue;
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if (addn_fifo > rem_fifo) {
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netdev_warn(pdata->netdev,
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"RXq%u cannot set needed fifo size\n", i);
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if (!rem_fifo)
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continue;
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addn_fifo = rem_fifo;
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}
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fifo[i] += (addn_fifo / XGMAC_FIFO_UNIT);
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rem_fifo -= addn_fifo;
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}
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if (rem_fifo) {
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unsigned int inc_fifo = rem_fifo / prio_queues;
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/* Distribute remaining fifo across queues */
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for (i = 0; i < prio_queues; i++)
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fifo[i] += (inc_fifo / XGMAC_FIFO_UNIT);
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}
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}
|
||||
|
||||
static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
unsigned int fifo_size;
|
||||
|
|
@ -2059,25 +2202,50 @@ static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
|
|||
|
||||
netif_info(pdata, drv, pdata->netdev,
|
||||
"%d Tx hardware queues, %d byte fifo per queue\n",
|
||||
pdata->tx_q_count, ((fifo[0] + 1) * 256));
|
||||
pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT));
|
||||
}
|
||||
|
||||
static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
unsigned int fifo_size;
|
||||
unsigned int fifo[XGBE_MAX_QUEUES];
|
||||
unsigned int prio_queues;
|
||||
unsigned int i;
|
||||
|
||||
fifo_size = xgbe_get_rx_fifo_size(pdata);
|
||||
/* Clear any DCB related fifo/queue information */
|
||||
memset(pdata->pfcq, 0, sizeof(pdata->pfcq));
|
||||
pdata->pfc_rfa = 0;
|
||||
|
||||
xgbe_calculate_equal_fifo(fifo_size, pdata->rx_q_count, fifo);
|
||||
fifo_size = xgbe_get_rx_fifo_size(pdata);
|
||||
prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
|
||||
|
||||
/* Assign a minimum fifo to the non-VLAN priority queues */
|
||||
fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo);
|
||||
|
||||
if (pdata->pfc && pdata->ets)
|
||||
xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo);
|
||||
else
|
||||
xgbe_calculate_equal_fifo(fifo_size, prio_queues, fifo);
|
||||
|
||||
for (i = 0; i < pdata->rx_q_count; i++)
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]);
|
||||
|
||||
netif_info(pdata, drv, pdata->netdev,
|
||||
"%d Rx hardware queues, %d byte fifo per queue\n",
|
||||
pdata->rx_q_count, ((fifo[0] + 1) * 256));
|
||||
xgbe_calculate_flow_control_threshold(pdata, fifo);
|
||||
xgbe_config_flow_control_threshold(pdata);
|
||||
|
||||
if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) {
|
||||
netif_info(pdata, drv, pdata->netdev,
|
||||
"%u Rx hardware queues\n", pdata->rx_q_count);
|
||||
for (i = 0; i < pdata->rx_q_count; i++)
|
||||
netif_info(pdata, drv, pdata->netdev,
|
||||
"RxQ%u, %u byte fifo queue\n", i,
|
||||
((fifo[i] + 1) * XGMAC_FIFO_UNIT));
|
||||
} else {
|
||||
netif_info(pdata, drv, pdata->netdev,
|
||||
"%u Rx hardware queues, %u byte fifo per queue\n",
|
||||
pdata->rx_q_count,
|
||||
((fifo[0] + 1) * XGMAC_FIFO_UNIT));
|
||||
}
|
||||
}
|
||||
|
||||
static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
|
||||
|
|
@ -2113,8 +2281,7 @@ static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
|
|||
}
|
||||
|
||||
/* Map the 8 VLAN priority values to available MTL Rx queues */
|
||||
prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
|
||||
pdata->rx_q_count);
|
||||
prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count);
|
||||
ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
|
||||
ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
|
||||
|
||||
|
|
@ -2162,16 +2329,120 @@ static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
|
|||
}
|
||||
}
|
||||
|
||||
static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
|
||||
static void xgbe_config_tc(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned int offset, queue, prio;
|
||||
u8 i;
|
||||
|
||||
for (i = 0; i < pdata->rx_q_count; i++) {
|
||||
/* Activate flow control when less than 4k left in fifo */
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
|
||||
netdev_reset_tc(pdata->netdev);
|
||||
if (!pdata->num_tcs)
|
||||
return;
|
||||
|
||||
/* De-activate flow control when more than 6k left in fifo */
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
|
||||
netdev_set_num_tc(pdata->netdev, pdata->num_tcs);
|
||||
|
||||
for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) {
|
||||
while ((queue < pdata->tx_q_count) &&
|
||||
(pdata->q2tc_map[queue] == i))
|
||||
queue++;
|
||||
|
||||
netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n",
|
||||
i, offset, queue - 1);
|
||||
netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset);
|
||||
offset = queue;
|
||||
}
|
||||
|
||||
if (!pdata->ets)
|
||||
return;
|
||||
|
||||
for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
|
||||
netdev_set_prio_tc_map(pdata->netdev, prio,
|
||||
pdata->ets->prio_tc[prio]);
|
||||
}
|
||||
|
||||
static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
struct ieee_ets *ets = pdata->ets;
|
||||
unsigned int total_weight, min_weight, weight;
|
||||
unsigned int mask, reg, reg_val;
|
||||
unsigned int i, prio;
|
||||
|
||||
if (!ets)
|
||||
return;
|
||||
|
||||
/* Set Tx to deficit weighted round robin scheduling algorithm (when
|
||||
* traffic class is using ETS algorithm)
|
||||
*/
|
||||
XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
|
||||
|
||||
/* Set Traffic Class algorithms */
|
||||
total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
|
||||
min_weight = total_weight / 100;
|
||||
if (!min_weight)
|
||||
min_weight = 1;
|
||||
|
||||
for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
|
||||
/* Map the priorities to the traffic class */
|
||||
mask = 0;
|
||||
for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
|
||||
if (ets->prio_tc[prio] == i)
|
||||
mask |= (1 << prio);
|
||||
}
|
||||
mask &= 0xff;
|
||||
|
||||
netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n",
|
||||
i, mask);
|
||||
reg = MTL_TCPM0R + (MTL_TCPM_INC * (i / MTL_TCPM_TC_PER_REG));
|
||||
reg_val = XGMAC_IOREAD(pdata, reg);
|
||||
|
||||
reg_val &= ~(0xff << ((i % MTL_TCPM_TC_PER_REG) << 3));
|
||||
reg_val |= (mask << ((i % MTL_TCPM_TC_PER_REG) << 3));
|
||||
|
||||
XGMAC_IOWRITE(pdata, reg, reg_val);
|
||||
|
||||
/* Set the traffic class algorithm */
|
||||
switch (ets->tc_tsa[i]) {
|
||||
case IEEE_8021QAZ_TSA_STRICT:
|
||||
netif_dbg(pdata, drv, pdata->netdev,
|
||||
"TC%u using SP\n", i);
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
|
||||
MTL_TSA_SP);
|
||||
break;
|
||||
case IEEE_8021QAZ_TSA_ETS:
|
||||
weight = total_weight * ets->tc_tx_bw[i] / 100;
|
||||
weight = clamp(weight, min_weight, total_weight);
|
||||
|
||||
netif_dbg(pdata, drv, pdata->netdev,
|
||||
"TC%u using DWRR (weight %u)\n", i, weight);
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
|
||||
MTL_TSA_ETS);
|
||||
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
|
||||
weight);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
xgbe_config_tc(pdata);
|
||||
}
|
||||
|
||||
static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
|
||||
/* Just stop the Tx queues while Rx fifo is changed */
|
||||
netif_tx_stop_all_queues(pdata->netdev);
|
||||
|
||||
/* Suspend Rx so that fifo's can be adjusted */
|
||||
pdata->hw_if.disable_rx(pdata);
|
||||
}
|
||||
|
||||
xgbe_config_rx_fifo_size(pdata);
|
||||
xgbe_config_flow_control(pdata);
|
||||
|
||||
if (!test_bit(XGBE_DOWN, &pdata->dev_state)) {
|
||||
/* Resume Rx */
|
||||
pdata->hw_if.enable_rx(pdata);
|
||||
|
||||
/* Resume Tx queues */
|
||||
netif_tx_start_all_queues(pdata->netdev);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2879,12 +3150,10 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
|
|||
xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
|
||||
xgbe_config_tx_fifo_size(pdata);
|
||||
xgbe_config_rx_fifo_size(pdata);
|
||||
xgbe_config_flow_control_threshold(pdata);
|
||||
/*TODO: Error Packet and undersized good Packet forwarding enable
|
||||
(FEP and FUP)
|
||||
*/
|
||||
xgbe_config_dcb_tc(pdata);
|
||||
xgbe_config_dcb_pfc(pdata);
|
||||
xgbe_enable_mtl_interrupts(pdata);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -158,6 +158,7 @@
|
|||
|
||||
#define XGBE_MAX_DMA_CHANNELS 16
|
||||
#define XGBE_MAX_QUEUES 16
|
||||
#define XGBE_PRIORITY_QUEUES 8
|
||||
#define XGBE_DMA_STOP_TIMEOUT 5
|
||||
|
||||
/* DMA cache settings - Outer sharable, write-back, write-allocate */
|
||||
|
|
@ -177,6 +178,13 @@
|
|||
#define XGMAC_MAX_STD_PACKET 1518
|
||||
#define XGMAC_JUMBO_PACKET_MTU 9000
|
||||
#define XGMAC_MAX_JUMBO_PACKET 9018
|
||||
#define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
|
||||
|
||||
#define XGMAC_PFC_DATA_LEN 46
|
||||
#define XGMAC_PFC_DELAYS 14000
|
||||
|
||||
#define XGMAC_PRIO_QUEUES(_cnt) \
|
||||
min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
|
||||
|
||||
/* Common property names */
|
||||
#define XGBE_MAC_ADDR_PROPERTY "mac-address"
|
||||
|
|
@ -210,6 +218,12 @@
|
|||
|
||||
#define XGMAC_FIFO_RX_MAX 81920
|
||||
#define XGMAC_FIFO_TX_MAX 81920
|
||||
#define XGMAC_FIFO_MIN_ALLOC 2048
|
||||
#define XGMAC_FIFO_UNIT 256
|
||||
#define XGMAC_FIFO_ALIGN(_x) \
|
||||
(((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
|
||||
#define XGMAC_FIFO_FC_OFF 2048
|
||||
#define XGMAC_FIFO_FC_MIN 4096
|
||||
|
||||
#define XGBE_TC_MIN_QUANTUM 10
|
||||
|
||||
|
|
@ -234,6 +248,14 @@
|
|||
/* Flow control queue count */
|
||||
#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
|
||||
|
||||
/* Flow control threshold units */
|
||||
#define XGMAC_FLOW_CONTROL_UNIT 512
|
||||
#define XGMAC_FLOW_CONTROL_ALIGN(_x) \
|
||||
(((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
|
||||
#define XGMAC_FLOW_CONTROL_VALUE(_x) \
|
||||
(((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
|
||||
#define XGMAC_FLOW_CONTROL_MAX 33280
|
||||
|
||||
/* Maximum MAC address hash table size (256 bits = 8 bytes) */
|
||||
#define XGBE_MAC_HASH_TABLE_SIZE 8
|
||||
|
||||
|
|
@ -843,6 +865,8 @@ struct xgbe_prv_data {
|
|||
unsigned int pause_autoneg;
|
||||
unsigned int tx_pause;
|
||||
unsigned int rx_pause;
|
||||
unsigned int rx_rfa[XGBE_MAX_QUEUES];
|
||||
unsigned int rx_rfd[XGBE_MAX_QUEUES];
|
||||
|
||||
/* Receive Side Scaling settings */
|
||||
u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
|
||||
|
|
@ -882,6 +906,8 @@ struct xgbe_prv_data {
|
|||
struct ieee_pfc *pfc;
|
||||
unsigned int q2tc_map[XGBE_MAX_QUEUES];
|
||||
unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
|
||||
unsigned int pfcq[XGBE_MAX_QUEUES];
|
||||
unsigned int pfc_rfa;
|
||||
u8 num_tcs;
|
||||
|
||||
/* Hardware features of the device */
|
||||
|
|
|
|||
Loading…
Reference in New Issue