ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In reality there are a number of differences to the actual Armada-XP so rather than including armada-xp.dtsi and disabling many of the IP blocks. Include armada-370-xp.dtsi and add the required nodes. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>hifive-unleashed-5.1
Chris Packham
Gregory CLEMENT
parent
35a647f12c
commit
43e28ba877
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@ -45,11 +45,14 @@
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* common to all Armada XP SoCs.
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*/
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#include "armada-xp.dtsi"
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#include "armada-370-xp.dtsi"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Marvell 98DX3236 SoC";
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compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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@ -72,12 +75,19 @@
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};
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
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MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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/*
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* 98DX3236 has 1 x1 PCIe unit Gen2.0
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*/
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@ -117,48 +127,18 @@
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};
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internal-regs {
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,mv98dx3236-core-clock";
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sdramc@1400 {
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compatible = "marvell,armada-xp-sdram-controller";
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reg = <0x1400 0x500>;
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};
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cpuclk: clock-complex@18700 {
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compatible = "marvell,mv98dx3236-cpu-clock";
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};
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corediv-clock@18740 {
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status = "disabled";
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};
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xor@60900 {
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status = "disabled";
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};
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crypto@90000 {
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status = "disabled";
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};
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xor@f0900 {
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status = "disabled";
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};
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xor@f0800 {
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compatible = "marvell,orion-xor";
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reg = <0xf0800 0x100
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0xf0a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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L2: l2-cache@8000 {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-level = <2>;
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cache-unified;
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wt-override;
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};
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gpio0: gpio@18100 {
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@ -190,9 +170,91 @@
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interrupts = <87>;
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};
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systemc: system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,mv98dx3236-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,mv98dx3236-cpu-clock";
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reg = <0x18700 0x24>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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};
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corediv-clock@18740 {
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status = "disabled";
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};
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
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};
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ethernet@70000 {
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compatible = "marvell,armada-xp-neta";
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};
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ethernet@74000 {
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compatible = "marvell,armada-xp-neta";
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};
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xor1: xor@f0800 {
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compatible = "marvell,orion-xor";
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reg = <0xf0800 0x100
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0xf0a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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nand: nand@d0000 {
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clocks = <&dfx_coredivclk 0>;
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};
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xor0: xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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};
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dfx: dfx-server@ac000000 {
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@ -225,6 +287,53 @@
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};
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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&i2c0 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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};
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&i2c1 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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&mpic {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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&timer {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&watchdog {
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compatible = "marvell,armada-xp-wdt";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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&cpurst {
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reg = <0x20800 0x20>;
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};
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&usb0 {
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clocks = <&gateclk 18>;
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};
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&usb1 {
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clocks = <&gateclk 19>;
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};
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&pinctrl {
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@ -237,14 +346,13 @@
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};
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};
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&spi0 {
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compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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};
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&sdio {
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status = "disabled";
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};
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&crypto_sram0 {
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status = "disabled";
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};
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&crypto_sram1 {
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status = "disabled";
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};
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@ -49,7 +49,7 @@
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/ {
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model = "Marvell 98DX3336 SoC";
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compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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cpus {
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cpu@1 {
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@ -49,7 +49,7 @@
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/ {
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model = "Marvell 98DX4251 SoC";
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compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armadaxp", "marvell,armada-370-xp";
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compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
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cpus {
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cpu@1 {
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@ -58,7 +58,7 @@
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/ {
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model = "Marvell Bobcat2 Evaluation Board";
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compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armadaxp", "marvell,armada-370-xp";
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compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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@ -58,7 +58,7 @@
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/ {
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model = "DB-XC3-24G4XG";
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compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armadaxp", "marvell,armada-370-xp";
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compatible = "marvell,db-xc3-24g4xg", "marvell,armadaxp-98dx3336", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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