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mailbox changes for v5.5 

- omap : misc - catch error returned from pm_runtime_put_sync
 - hisi : misc - drop .owner from platform_driver
 - stm : change how wakeup is handled
 - imx : fix - bailout on error and nuke correct irq
 - imx : add support for imx7ulp platform
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Merge tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:

 - omap : misc - catch error returned from pm_runtime_put_sync

 - hisi : misc - drop .owner from platform_driver

 - stm : change how wakeup is handled

 - imx : fix - bailout on error and nuke correct irq

 - imx : add support for imx7ulp platform

* tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: imx: add support for imx v1 mu
  dt-bindings: mailbox: imx-mu: add imx7ulp MU support
  mailbox: imx: Clear the right interrupts at shutdown
  mailbox: imx: Fix Tx doorbell shutdown path
  mailbox: stm32-ipcc: Update wakeup management
  mailbox: no need to set .owner platform_driver_register
  mailbox/omap: Handle if CONFIG_PM is disabled
alistair/sunxi64-5.5-dsi
Linus Torvalds 2019-12-01 18:42:02 -08:00
parent 454d9c4aa7 c6c6bc6ea9
commit 43fd4bd72c
5 changed files with 64 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/mailbox/fsl,mu.txt
View File

@ -21,6 +21,8 @@ Required properties:
imx6sx, imx7s, imx8qxp, imx8qm.
The "fsl,imx6sx-mu" compatible is seen as generic and should
be included together with SoC specific compatible.
There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
compatible to support it.
- reg : Should contain the registers location and length
- interrupts : Interrupt number. The interrupt specifier format depends
on the interrupt controller parent.

1
drivers/mailbox/hi6220-mailbox.c
View File

@ -354,7 +354,6 @@ static int hi6220_mbox_probe(struct platform_device *pdev)
static struct platform_driver hi6220_mbox_driver = {
.driver = {
.name = "hi6220-mbox",
.owner = THIS_MODULE,
.of_match_table = hi6220_mbox_of_match,
},
.probe = hi6220_mbox_probe,

74
drivers/mailbox/imx-mailbox.c
View File

@ -12,19 +12,11 @@
#include <linux/of_device.h>
#include <linux/slab.h>
/* Transmit Register */
#define IMX_MU_xTRn(x) (0x00 + 4 * (x))
/* Receive Register */
#define IMX_MU_xRRn(x) (0x10 + 4 * (x))
/* Status Register */
#define IMX_MU_xSR 0x20
#define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
#define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
#define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
#define IMX_MU_xSR_BRDIP BIT(9)
/* Control Register */
#define IMX_MU_xCR 0x24
/* General Purpose Interrupt Enable */
#define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
/* Receive Interrupt Enable */
@ -44,6 +36,13 @@ enum imx_mu_chan_type {
IMX_MU_TYPE_RXDB, /* Rx doorbell */
};
struct imx_mu_dcfg {
u32 xTR[4]; /* Transmit Registers */
u32 xRR[4]; /* Receive Registers */
u32 xSR; /* Status Register */
u32 xCR; /* Control Register */
};
struct imx_mu_con_priv {
unsigned int idx;
char irq_desc[IMX_MU_CHAN_NAME_SIZE];
@ -61,12 +60,27 @@ struct imx_mu_priv {
struct mbox_chan mbox_chans[IMX_MU_CHANS];
struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
const struct imx_mu_dcfg *dcfg;
struct clk *clk;
int irq;
bool side_b;
};
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.xTR = {0x0, 0x4, 0x8, 0xc},
.xRR = {0x10, 0x14, 0x18, 0x1c},
.xSR = 0x20,
.xCR = 0x24,
};
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xTR = {0x20, 0x24, 0x28, 0x2c},
.xRR = {0x40, 0x44, 0x48, 0x4c},
.xSR = 0x60,
.xCR = 0x64,
};
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
{
return container_of(mbox, struct imx_mu_priv, mbox);
@ -88,10 +102,10 @@ static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
u32 val;
spin_lock_irqsave(&priv->xcr_lock, flags);
val = imx_mu_read(priv, IMX_MU_xCR);
val = imx_mu_read(priv, priv->dcfg->xCR);
val &= ~clr;
val |= set;
imx_mu_write(priv, val, IMX_MU_xCR);
imx_mu_write(priv, val, priv->dcfg->xCR);
spin_unlock_irqrestore(&priv->xcr_lock, flags);
return val;
@ -111,8 +125,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
struct imx_mu_con_priv *cp = chan->con_priv;
u32 val, ctrl, dat;
ctrl = imx_mu_read(priv, IMX_MU_xCR);
val = imx_mu_read(priv, IMX_MU_xSR);
ctrl = imx_mu_read(priv, priv->dcfg->xCR);
val = imx_mu_read(priv, priv->dcfg->xSR);
switch (cp->type) {
case IMX_MU_TYPE_TX:
@ -138,10 +152,10 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
mbox_chan_txdone(chan, 0);
} else if (val == IMX_MU_xSR_RFn(cp->idx)) {
dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx));
dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
mbox_chan_received_data(chan, (void *)&dat);
} else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR);
imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
mbox_chan_received_data(chan, NULL);
} else {
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
@ -159,7 +173,7 @@ static int imx_mu_send_data(struct mbox_chan *chan, void *data)
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx));
imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
break;
case IMX_MU_TYPE_TXDB:
@ -214,11 +228,24 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
if (cp->type == IMX_MU_TYPE_TXDB)
if (cp->type == IMX_MU_TYPE_TXDB) {
tasklet_kill(&cp->txdb_tasklet);
return;
}
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx) |
IMX_MU_xCR_RIEn(cp->idx) | IMX_MU_xCR_GIEn(cp->idx));
switch (cp->type) {
case IMX_MU_TYPE_TX:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
break;
case IMX_MU_TYPE_RX:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
break;
case IMX_MU_TYPE_RXDB:
imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
break;
default:
break;
}
free_irq(priv->irq, chan);
}
@ -257,7 +284,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
return;
/* Set default MU configuration */
imx_mu_write(priv, 0, IMX_MU_xCR);
imx_mu_write(priv, 0, priv->dcfg->xCR);
}
static int imx_mu_probe(struct platform_device *pdev)
@ -265,6 +292,7 @@ static int imx_mu_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct imx_mu_priv *priv;
const struct imx_mu_dcfg *dcfg;
unsigned int i;
int ret;
@ -282,6 +310,11 @@ static int imx_mu_probe(struct platform_device *pdev)
if (priv->irq < 0)
return priv->irq;
dcfg = of_device_get_match_data(dev);
if (!dcfg)
return -EINVAL;
priv->dcfg = dcfg;
priv->clk = devm_clk_get(dev, NULL);
if (IS_ERR(priv->clk)) {
if (PTR_ERR(priv->clk) != -ENOENT)
@ -335,7 +368,8 @@ static int imx_mu_remove(struct platform_device *pdev)
}
static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx6sx-mu" },
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
{ },
};
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);

2
drivers/mailbox/omap-mailbox.c
View File

@ -868,7 +868,7 @@ static int omap_mbox_probe(struct platform_device *pdev)
dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
ret = pm_runtime_put_sync(mdev->dev);
if (ret < 0)
if (ret < 0 && ret != -ENOSYS)
goto unregister;
devm_kfree(&pdev->dev, finfoblk);

36
drivers/mailbox/stm32-ipcc.c
View File

@ -52,7 +52,6 @@ struct stm32_ipcc {
struct clk *clk;
spinlock_t lock; /* protect access to IPCC registers */
int irqs[IPCC_IRQ_NUM];
int wkp;
u32 proc_id;
u32 n_chans;
u32 xcr;
@ -282,16 +281,9 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
/* wakeup */
if (of_property_read_bool(np, "wakeup-source")) {
ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
if (ipcc->wkp < 0) {
if (ipcc->wkp != -EPROBE_DEFER)
dev_err(dev, "could not get wakeup IRQ\n");
ret = ipcc->wkp;
goto err_clk;
}
device_set_wakeup_capable(dev, true);
ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
if (ret) {
dev_err(dev, "Failed to set wake up irq\n");
goto err_init_wkp;
@ -334,10 +326,10 @@ static int stm32_ipcc_probe(struct platform_device *pdev)
return 0;
err_irq_wkp:
if (ipcc->wkp)
if (of_property_read_bool(np, "wakeup-source"))
dev_pm_clear_wake_irq(dev);
err_init_wkp:
device_init_wakeup(dev, false);
device_set_wakeup_capable(dev, false);
err_clk:
clk_disable_unprepare(ipcc->clk);
return ret;
@ -345,27 +337,17 @@ err_clk:
static int stm32_ipcc_remove(struct platform_device *pdev)
{
struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
struct device *dev = &pdev->dev;
if (ipcc->wkp)
if (of_property_read_bool(dev->of_node, "wakeup-source"))
dev_pm_clear_wake_irq(&pdev->dev);
device_init_wakeup(&pdev->dev, false);
device_set_wakeup_capable(dev, false);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
{
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
unsigned int i;
if (device_may_wakeup(dev))
for (i = 0; i < IPCC_IRQ_NUM; i++)
irq_set_irq_wake(ipcc->irqs[i], enable);
}
static int stm32_ipcc_suspend(struct device *dev)
{
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
@ -373,8 +355,6 @@ static int stm32_ipcc_suspend(struct device *dev)
ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
stm32_ipcc_set_irq_wake(dev, true);
return 0;
}
@ -382,8 +362,6 @@ static int stm32_ipcc_resume(struct device *dev)
{
struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
stm32_ipcc_set_irq_wake(dev, false);
writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);