MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
Get rid of a bunch of useless inline declarations, and join a bunch of improperly split lines. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Ingo Molnar <mingo@elte.hu> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2793/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -118,10 +118,9 @@ struct mips_pmu {
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static const struct mips_pmu *mipspmu;
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static int
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mipspmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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static int mipspmu_event_set_period(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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s64 left = local64_read(&hwc->period_left);
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@ -162,8 +161,8 @@ mipspmu_event_set_period(struct perf_event *event,
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}
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static void mipspmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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struct hw_perf_event *hwc,
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int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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unsigned long flags;
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@ -420,8 +419,7 @@ static struct pmu pmu = {
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.read = mipspmu_read,
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};
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static inline unsigned int
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mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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{
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/*
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* Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
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@ -437,8 +435,7 @@ mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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#endif
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}
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static const struct mips_perf_event *
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mipspmu_map_general_event(int idx)
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static const struct mips_perf_event *mipspmu_map_general_event(int idx)
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{
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const struct mips_perf_event *pev;
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@ -449,8 +446,7 @@ mipspmu_map_general_event(int idx)
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return pev;
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}
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static const struct mips_perf_event *
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mipspmu_map_cache_event(u64 config)
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static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
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{
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unsigned int cache_type, cache_op, cache_result;
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const struct mips_perf_event *pev;
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@ -513,9 +509,9 @@ static int validate_group(struct perf_event *event)
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}
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/* This is needed by specific irq handlers in perf_event_*.c */
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static void
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handle_associated_event(struct cpu_hw_events *cpuc,
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int idx, struct perf_sample_data *data, struct pt_regs *regs)
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static void handle_associated_event(struct cpu_hw_events *cpuc,
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int idx, struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct perf_event *event = cpuc->events[idx];
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struct hw_perf_event *hwc = &event->hw;
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@ -49,37 +49,32 @@ static int cpu_has_mipsmt_pertccounters;
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#endif
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/* Copied from op_model_mipsxx.c */
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static inline unsigned int vpe_shift(void)
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static unsigned int vpe_shift(void)
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{
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if (num_possible_cpus() > 1)
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return 1;
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return 0;
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}
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#else /* !CONFIG_MIPS_MT_SMP */
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#define vpe_id() 0
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static inline unsigned int vpe_shift(void)
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{
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return 0;
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}
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#endif /* CONFIG_MIPS_MT_SMP */
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static inline unsigned int
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counters_total_to_per_cpu(unsigned int counters)
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static unsigned int counters_total_to_per_cpu(unsigned int counters)
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{
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return counters >> vpe_shift();
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}
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static inline unsigned int
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counters_per_cpu_to_total(unsigned int counters)
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static unsigned int counters_per_cpu_to_total(unsigned int counters)
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{
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return counters << vpe_shift();
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}
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#else /* !CONFIG_MIPS_MT_SMP */
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#define vpe_id() 0
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#endif /* CONFIG_MIPS_MT_SMP */
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#define __define_perf_accessors(r, n, np) \
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\
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static inline unsigned int r_c0_ ## r ## n(void) \
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static unsigned int r_c0_ ## r ## n(void) \
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{ \
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unsigned int cpu = vpe_id(); \
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\
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@ -94,7 +89,7 @@ static inline unsigned int r_c0_ ## r ## n(void) \
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return 0; \
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} \
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\
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static inline void w_c0_ ## r ## n(unsigned int value) \
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static void w_c0_ ## r ## n(unsigned int value) \
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{ \
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unsigned int cpu = vpe_id(); \
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\
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@ -121,7 +116,7 @@ __define_perf_accessors(perfctrl, 1, 3)
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__define_perf_accessors(perfctrl, 2, 0)
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__define_perf_accessors(perfctrl, 3, 1)
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static inline int __n_counters(void)
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static int __n_counters(void)
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{
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if (!(read_c0_config1() & M_CONFIG1_PC))
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return 0;
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@ -135,7 +130,7 @@ static inline int __n_counters(void)
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return 4;
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}
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static inline int n_counters(void)
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static int n_counters(void)
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{
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int counters;
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@ -175,8 +170,7 @@ static void reset_counters(void *arg)
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}
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}
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static inline u64
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mipsxx_pmu_read_counter(unsigned int idx)
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static u64 mipsxx_pmu_read_counter(unsigned int idx)
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{
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switch (idx) {
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case 0:
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@ -193,8 +187,7 @@ mipsxx_pmu_read_counter(unsigned int idx)
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}
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}
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static inline void
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mipsxx_pmu_write_counter(unsigned int idx, u64 val)
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static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
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{
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switch (idx) {
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case 0:
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@ -212,8 +205,7 @@ mipsxx_pmu_write_counter(unsigned int idx, u64 val)
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}
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}
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static inline unsigned int
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mipsxx_pmu_read_control(unsigned int idx)
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static unsigned int mipsxx_pmu_read_control(unsigned int idx)
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{
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switch (idx) {
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case 0:
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@ -230,8 +222,7 @@ mipsxx_pmu_read_control(unsigned int idx)
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}
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}
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static inline void
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mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
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static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
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{
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switch (idx) {
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case 0:
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@ -511,9 +502,8 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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};
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#ifdef CONFIG_MIPS_MT_SMP
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static void
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check_and_calc_range(struct perf_event *event,
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const struct mips_perf_event *pev)
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static void check_and_calc_range(struct perf_event *event,
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const struct mips_perf_event *pev)
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{
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struct hw_perf_event *hwc = &event->hw;
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@ -536,9 +526,8 @@ check_and_calc_range(struct perf_event *event,
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hwc->config_base |= M_TC_EN_ALL;
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}
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#else
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static void
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check_and_calc_range(struct perf_event *event,
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const struct mips_perf_event *pev)
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static void check_and_calc_range(struct perf_event *event,
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const struct mips_perf_event *pev)
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{
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}
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#endif
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@ -733,8 +722,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
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return handled;
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}
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static irqreturn_t
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mipsxx_pmu_handle_irq(int irq, void *dev)
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static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
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{
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return mipsxx_pmu_handle_shared_irq();
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}
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@ -766,9 +754,8 @@ static void mipsxx_pmu_stop(void)
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#endif
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}
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static int
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mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc)
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static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
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struct hw_perf_event *hwc)
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{
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int i;
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@ -797,8 +784,7 @@ mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
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return -EAGAIN;
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}
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static void
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mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
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static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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unsigned long flags;
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@ -816,8 +802,7 @@ mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
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local_irq_restore(flags);
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}
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static void
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mipsxx_pmu_disable_event(int idx)
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static void mipsxx_pmu_disable_event(int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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unsigned long flags;
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@ -892,8 +877,7 @@ mipsxx_pmu_disable_event(int idx)
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* then 128 needs to be added to 15 as the input for the event config,
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* i.e., 143 (0x8F) to be used.
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*/
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static const struct mips_perf_event *
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mipsxx_pmu_map_raw_event(u64 config)
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static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
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{
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unsigned int raw_id = config & 0xff;
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unsigned int base_id = raw_id & 0x7f;
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