drm/radeon: improve GPU lockup debugging info on r6xx/r7xx/r8xx/r9xx
Print various CP register that have valuable informations regarding GPU lockup. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
4dbdf0aea9
commit
440a7cd87e
|
@ -2316,6 +2316,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
evergreen_mc_stop(rdev, &save);
|
||||
if (evergreen_mc_wait_for_idle(rdev)) {
|
||||
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
||||
|
@ -2353,6 +2361,14 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
evergreen_mc_resume(rdev, &save);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -88,6 +88,10 @@
|
|||
#define CONFIG_MEMSIZE 0x5428
|
||||
|
||||
#define CP_COHER_BASE 0x85F8
|
||||
#define CP_STALLED_STAT1 0x8674
|
||||
#define CP_STALLED_STAT2 0x8678
|
||||
#define CP_BUSY_STAT 0x867C
|
||||
#define CP_STAT 0x8680
|
||||
#define CP_ME_CNTL 0x86D8
|
||||
#define CP_ME_HALT (1 << 28)
|
||||
#define CP_PFP_HALT (1 << 26)
|
||||
|
|
|
@ -1122,6 +1122,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
|
||||
RREG32(0x14F8));
|
||||
dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
|
||||
|
@ -1170,6 +1178,14 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
evergreen_mc_resume(rdev, &save);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -236,6 +236,10 @@
|
|||
#define CP_SEM_WAIT_TIMER 0x85BC
|
||||
#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
|
||||
#define CP_COHER_CNTL2 0x85E8
|
||||
#define CP_STALLED_STAT1 0x8674
|
||||
#define CP_STALLED_STAT2 0x8678
|
||||
#define CP_BUSY_STAT 0x867C
|
||||
#define CP_STAT 0x8680
|
||||
#define CP_ME_CNTL 0x86D8
|
||||
#define CP_ME_HALT (1 << 28)
|
||||
#define CP_PFP_HALT (1 << 26)
|
||||
|
|
|
@ -1289,6 +1289,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(R_008014_GRBM_STATUS2));
|
||||
dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
|
||||
RREG32(R_000E50_SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
rv515_mc_stop(rdev, &save);
|
||||
if (r600_mc_wait_for_idle(rdev)) {
|
||||
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
||||
|
@ -1332,6 +1340,14 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
|
|||
RREG32(R_008014_GRBM_STATUS2));
|
||||
dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
|
||||
RREG32(R_000E50_SRBM_STATUS));
|
||||
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT1));
|
||||
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
|
||||
RREG32(CP_STALLED_STAT2));
|
||||
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
|
||||
RREG32(CP_BUSY_STAT));
|
||||
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
|
||||
RREG32(CP_STAT));
|
||||
rv515_mc_resume(rdev, &save);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -153,6 +153,9 @@
|
|||
|
||||
#define CONFIG_MEMSIZE 0x5428
|
||||
#define CONFIG_CNTL 0x5424
|
||||
#define CP_STALLED_STAT1 0x8674
|
||||
#define CP_STALLED_STAT2 0x8678
|
||||
#define CP_BUSY_STAT 0x867C
|
||||
#define CP_STAT 0x8680
|
||||
#define CP_COHER_BASE 0x85F8
|
||||
#define CP_DEBUG 0xC1FC
|
||||
|
|
Loading…
Reference in a new issue