sh: Fix up L2 cache probe.
SH7723 is the first hard silicon to implement the L2, and unsurprisingly, does the precise inverse of what the specification alleges. XOR the URAM/L2 size bits to get back in line with the existing parsing logic. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void)
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* SH-4A's have an optional PIPT L2.
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*/
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if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
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/* Bug if we can't decode the L2 info */
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BUG_ON(!(cvr & 0xf));
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/* Silicon and specifications have clearly never met.. */
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cvr ^= 0xf;
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/*
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* Size calculation is much more sensible
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* than it is for the L1.
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