Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Adjust CMCI mask on CPU hotplug [IA64] make flush_tlb_kernel_range() an inline function [IA64] Guard elfcorehdr_addr with #if CONFIG_PROC_FS [IA64] Fix Altix BTE error return status [IA64] Remove assembler warnings on head.S [IA64] Remove compiler warinings about uninitialized variable in irq_ia64.c [IA64] set_thread_area fails in IA32 chroot [IA64] print kernel release in OOPS to make kerneloops.org happy [IA64] Two trivial spelling fixes [IA64] Avoid unnecessary TLB flushes when allocating memory [IA64] ia32 nopage [IA64] signal: remove redundant code in setup_sigcontext() IA64: Slim down __clear_bit_unlock
This commit is contained in:
commit
4486c5f510
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@ -2034,7 +2034,8 @@ sba_init(void)
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|||
if (!ia64_platform_is("hpzx1") && !ia64_platform_is("hpzx1_swiotlb"))
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return 0;
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#if defined(CONFIG_IA64_GENERIC) && defined(CONFIG_CRASH_DUMP)
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#if defined(CONFIG_IA64_GENERIC) && defined(CONFIG_CRASH_DUMP) && \
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defined(CONFIG_PROC_FS)
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/* If we are booting a kdump kernel, the sba_iommu will
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* cause devices that were not shutdown properly to MCA
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* as soon as they are turned back on. Our only option for
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|
|
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@ -52,33 +52,29 @@ extern struct page *ia32_shared_page[];
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extern unsigned long *ia32_gdt;
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extern struct page *ia32_gate_page;
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struct page *
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ia32_install_shared_page (struct vm_area_struct *vma, unsigned long address, int *type)
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int
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ia32_install_shared_page (struct vm_area_struct *vma, struct vm_fault *vmf)
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{
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struct page *pg = ia32_shared_page[smp_processor_id()];
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get_page(pg);
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if (type)
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*type = VM_FAULT_MINOR;
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return pg;
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vmf->page = ia32_shared_page[smp_processor_id()];
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get_page(vmf->page);
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return 0;
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}
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struct page *
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ia32_install_gate_page (struct vm_area_struct *vma, unsigned long address, int *type)
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int
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ia32_install_gate_page (struct vm_area_struct *vma, struct vm_fault *vmf)
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{
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struct page *pg = ia32_gate_page;
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get_page(pg);
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if (type)
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*type = VM_FAULT_MINOR;
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return pg;
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vmf->page = ia32_gate_page;
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get_page(vmf->page);
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return 0;
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}
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static struct vm_operations_struct ia32_shared_page_vm_ops = {
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.nopage = ia32_install_shared_page
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.fault = ia32_install_shared_page
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};
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static struct vm_operations_struct ia32_gate_page_vm_ops = {
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.nopage = ia32_install_gate_page
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.fault = ia32_install_gate_page
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};
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void
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@ -1176,6 +1176,7 @@ tlb_purge_done:
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RESTORE_REG(cr.dcr, r25, r17);;
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RESTORE_REG(cr.iva, r25, r17);;
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RESTORE_REG(cr.pta, r25, r17);;
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srlz.d;; // required not to violate RAW dependency
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RESTORE_REG(cr.itv, r25, r17);;
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RESTORE_REG(cr.pmv, r25, r17);;
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RESTORE_REG(cr.cmcv, r25, r17);;
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|
|
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@ -200,7 +200,7 @@ assign_irq_vector (int irq)
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{
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unsigned long flags;
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int vector, cpu;
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cpumask_t domain;
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cpumask_t domain = CPU_MASK_NONE;
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vector = -ENOSPC;
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@ -340,7 +340,7 @@ int create_irq(void)
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{
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unsigned long flags;
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int irq, vector, cpu;
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cpumask_t domain;
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cpumask_t domain = CPU_MASK_NONE;
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irq = vector = -ENOSPC;
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spin_lock_irqsave(&vector_lock, flags);
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|
|
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@ -75,6 +75,7 @@
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#include <linux/workqueue.h>
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#include <linux/cpumask.h>
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#include <linux/kdebug.h>
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#include <linux/cpu.h>
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#include <asm/delay.h>
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#include <asm/machvec.h>
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|
@ -1813,6 +1814,36 @@ ia64_mca_cpu_init(void *cpu_data)
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PAGE_KERNEL));
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}
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static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
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{
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unsigned long flags;
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local_irq_save(flags);
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if (!cmc_polling_enabled)
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ia64_mca_cmc_vector_enable(NULL);
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local_irq_restore(flags);
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}
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static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
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unsigned long action,
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void *hcpu)
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{
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int hotcpu = (unsigned long) hcpu;
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switch (action) {
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust,
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NULL, 1, 0);
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block mca_cpu_notifier __cpuinitdata = {
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.notifier_call = mca_cpu_callback
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};
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/*
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* ia64_mca_init
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*
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|
@ -1996,6 +2027,8 @@ ia64_mca_late_init(void)
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if (!mca_init)
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return 0;
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register_hotcpu_notifier(&mca_cpu_notifier);
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|
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/* Setup the CMCI/P vector and handler */
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init_timer(&cmc_poll_timer);
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cmc_poll_timer.function = ia64_mca_cmc_poll;
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|
|
|
@ -27,6 +27,7 @@
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/kdebug.h>
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#include <linux/utsname.h>
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#include <asm/cpu.h>
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#include <asm/delay.h>
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|
@ -107,8 +108,9 @@ show_regs (struct pt_regs *regs)
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print_modules();
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printk("\nPid: %d, CPU %d, comm: %20s\n", task_pid_nr(current),
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smp_processor_id(), current->comm);
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printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s\n",
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regs->cr_ipsr, regs->cr_ifs, ip, print_tainted());
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printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s (%s)\n",
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regs->cr_ipsr, regs->cr_ifs, ip, print_tainted(),
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init_utsname()->release);
|
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print_symbol("ip is at %s\n", ip);
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printk("unat: %016lx pfs : %016lx rsc : %016lx\n",
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regs->ar_unat, regs->ar_pfs, regs->ar_rsc);
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|
@ -737,6 +739,7 @@ flush_thread (void)
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ia32_drop_ia64_partial_page_list(current);
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||||
current->thread.task_size = IA32_PAGE_OFFSET;
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set_fs(USER_DS);
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memset(current->thread.tls_array, 0, sizeof(current->thread.tls_array));
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}
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#endif
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}
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|
|
|
@ -280,15 +280,7 @@ setup_sigcontext (struct sigcontext __user *sc, sigset_t *mask, struct sigscratc
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err |= __copy_to_user(&sc->sc_gr[15], &scr->pt.r15, 8); /* r15 */
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err |= __put_user(scr->pt.cr_iip + ia64_psr(&scr->pt)->ri, &sc->sc_ip);
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||||
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||||
if (flags & IA64_SC_FLAG_IN_SYSCALL) {
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||||
/* Clear scratch registers if the signal interrupted a system call. */
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err |= __put_user(0, &sc->sc_ar_ccv); /* ar.ccv */
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err |= __put_user(0, &sc->sc_br[7]); /* b7 */
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err |= __put_user(0, &sc->sc_gr[14]); /* r14 */
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err |= __clear_user(&sc->sc_ar25, 2*8); /* ar.csd & ar.ssd */
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err |= __clear_user(&sc->sc_gr[2], 2*8); /* r2-r3 */
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err |= __clear_user(&sc->sc_gr[16], 16*8); /* r16-r31 */
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||||
} else {
|
||||
if (!(flags & IA64_SC_FLAG_IN_SYSCALL)) {
|
||||
/* Copy scratch regs to sigcontext if the signal didn't interrupt a syscall. */
|
||||
err |= __put_user(scr->pt.ar_ccv, &sc->sc_ar_ccv); /* ar.ccv */
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err |= __put_user(scr->pt.b7, &sc->sc_br[7]); /* b7 */
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||||
|
|
|
@ -118,7 +118,7 @@ static int uncached_add_chunk(struct uncached_pool *uc_pool, int nid)
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for (i = 0; i < (IA64_GRANULE_SIZE / PAGE_SIZE); i++)
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SetPageUncached(&page[i]);
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flush_tlb_kernel_range(uc_addr, uc_adddr + IA64_GRANULE_SIZE);
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flush_tlb_kernel_range(uc_addr, uc_addr + IA64_GRANULE_SIZE);
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status = ia64_pal_prefetch_visibility(PAL_VISIBILITY_PHYSICAL);
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if (status == PAL_VISIBILITY_OK_REMOTE_NEEDED) {
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|
|
|
@ -10,6 +10,7 @@
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|||
* IPI based ptc implementation and A-step IPI implementation.
|
||||
* Rohit Seth <rohit.seth@intel.com>
|
||||
* Ken Chen <kenneth.w.chen@intel.com>
|
||||
* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
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||||
*/
|
||||
#include <linux/module.h>
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||||
#include <linux/init.h>
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||||
|
@ -89,9 +90,16 @@ ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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|||
{
|
||||
static DEFINE_SPINLOCK(ptcg_lock);
|
||||
|
||||
if (mm != current->active_mm || !current->mm) {
|
||||
flush_tlb_all();
|
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return;
|
||||
struct mm_struct *active_mm = current->active_mm;
|
||||
|
||||
if (mm != active_mm) {
|
||||
/* Restore region IDs for mm */
|
||||
if (mm && active_mm) {
|
||||
activate_context(mm);
|
||||
} else {
|
||||
flush_tlb_all();
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* HW requires global serialization of ptc.ga. */
|
||||
|
@ -107,6 +115,10 @@ ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
|
|||
} while (start < end);
|
||||
}
|
||||
spin_unlock(&ptcg_lock);
|
||||
|
||||
if (mm != active_mm) {
|
||||
activate_context(active_mm);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
@ -227,7 +227,7 @@ retry_bteop:
|
|||
BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
|
||||
|
||||
if (transfer_stat & IBLS_ERROR) {
|
||||
bte_status = transfer_stat & ~IBLS_ERROR;
|
||||
bte_status = BTE_GET_ERROR_STATUS(transfer_stat);
|
||||
} else {
|
||||
bte_status = BTE_SUCCESS;
|
||||
}
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
@ -148,7 +148,11 @@ int shub2_bte_error_handler(unsigned long _nodepda)
|
|||
for (i = 0; i < BTES_PER_NODE; i++) {
|
||||
bte = &err_nodepda->bte_if[i];
|
||||
status = BTE_LNSTAT_LOAD(bte);
|
||||
if ((status & IBLS_ERROR) || !(status & IBLS_BUSY))
|
||||
if (status & IBLS_ERROR) {
|
||||
bte->bh_error = BTE_SHUB2_ERROR(status);
|
||||
continue;
|
||||
}
|
||||
if (!(status & IBLS_BUSY))
|
||||
continue;
|
||||
mod_timer(recovery_timer, jiffies + (HZ * 5));
|
||||
BTE_PRINTK(("eh:%p:%d Marked Giving up\n", err_nodepda,
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
* } else
|
||||
* do desired mmr access
|
||||
*
|
||||
* According to hw, we can use reads instead of writes to the above addres
|
||||
* According to hw, we can use reads instead of writes to the above address
|
||||
*
|
||||
* Note this WAR can only to be used for accessing internal MMR's in the
|
||||
* TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff. This includes the
|
||||
|
|
|
@ -124,10 +124,21 @@ clear_bit_unlock (int nr, volatile void *addr)
|
|||
/**
|
||||
* __clear_bit_unlock - Non-atomically clear a bit with release
|
||||
*
|
||||
* This is like clear_bit_unlock, but the implementation may use a non-atomic
|
||||
* store (this one uses an atomic, however).
|
||||
* This is like clear_bit_unlock, but the implementation uses a store
|
||||
* with release semantics. See also __raw_spin_unlock().
|
||||
*/
|
||||
#define __clear_bit_unlock clear_bit_unlock
|
||||
static __inline__ void
|
||||
__clear_bit_unlock(int nr, volatile void *addr)
|
||||
{
|
||||
__u32 mask, new;
|
||||
volatile __u32 *m;
|
||||
|
||||
m = (volatile __u32 *)addr + (nr >> 5);
|
||||
mask = ~(1 << (nr & 31));
|
||||
new = *m & mask;
|
||||
barrier();
|
||||
ia64_st4_rel_nta(m, new);
|
||||
}
|
||||
|
||||
/**
|
||||
* __clear_bit - Clears a bit in memory (non-atomic version)
|
||||
|
|
|
@ -191,6 +191,11 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__;
|
|||
asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
|
||||
})
|
||||
|
||||
#define ia64_st4_rel_nta(m, val) \
|
||||
({ \
|
||||
asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
|
||||
})
|
||||
|
||||
#define ia64_stfs(x, regnum) \
|
||||
({ \
|
||||
register double __f__ asm ("f"#regnum); \
|
||||
|
|
|
@ -63,7 +63,7 @@ extern int ia64_last_device_vector;
|
|||
#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
|
||||
|
||||
#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */
|
||||
#define IA64_PERFMON_VECTOR 0xee /* performanc monitor interrupt vector */
|
||||
#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */
|
||||
#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
|
||||
#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
|
||||
#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */
|
||||
|
|
|
@ -110,6 +110,9 @@
|
|||
#define ia64_st4_rel __st4_rel
|
||||
#define ia64_st8_rel __st8_rel
|
||||
|
||||
/* FIXME: need st4.rel.nta intrinsic */
|
||||
#define ia64_st4_rel_nta __st4_rel
|
||||
|
||||
#define ia64_ld1_acq __ld1_acq
|
||||
#define ia64_ld2_acq __ld2_acq
|
||||
#define ia64_ld4_acq __ld4_acq
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 2000-2006 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
|
||||
|
@ -150,6 +150,35 @@ typedef enum {
|
|||
BTEFAIL_NOTAVAIL, /* BTE not available */
|
||||
} bte_result_t;
|
||||
|
||||
#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
|
||||
#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
|
||||
#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
|
||||
#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
|
||||
#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
|
||||
#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
|
||||
#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
|
||||
|
||||
#define BTE_ERR_BITS 0x3FUL
|
||||
#define BTE_ERR_SHIFT 36
|
||||
#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
|
||||
|
||||
#define BTE_ERROR_RETRY(value) \
|
||||
(is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
|
||||
: (value != BTEFAIL_TOUT))
|
||||
|
||||
/*
|
||||
* On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
|
||||
*/
|
||||
#define BTE_SHUB2_ERROR(_status) \
|
||||
((_status & BTE_ERR_MASK) \
|
||||
? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
|
||||
: _status)
|
||||
|
||||
#define BTE_GET_ERROR_STATUS(_status) \
|
||||
(BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
|
||||
|
||||
#define BTE_VALID_SH2_ERROR(value) \
|
||||
((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
|
||||
|
||||
/*
|
||||
* Structure defining a bte. An instance of this
|
||||
|
|
|
@ -86,7 +86,7 @@ xp_bte_copy(u64 src, u64 vdst, u64 len, u64 mode, void *notification)
|
|||
BUG_ON(REGION_NUMBER(vdst) != RGN_KERNEL);
|
||||
|
||||
ret = bte_copy(src, pdst, len, mode, notification);
|
||||
if (ret != BTE_SUCCESS) {
|
||||
if ((ret != BTE_SUCCESS) && BTE_ERROR_RETRY(ret)) {
|
||||
if (!in_interrupt()) {
|
||||
cond_resched();
|
||||
}
|
||||
|
@ -244,7 +244,30 @@ enum xpc_retval {
|
|||
|
||||
xpcDisconnected, /* 51: channel disconnected (closed) */
|
||||
|
||||
xpcUnknownReason /* 52: unknown reason -- must be last in list */
|
||||
xpcBteSh2Start, /* 52: BTE CRB timeout */
|
||||
|
||||
/* 53: 0x1 BTE Error Response Short */
|
||||
xpcBteSh2RspShort = xpcBteSh2Start + BTEFAIL_SH2_RESP_SHORT,
|
||||
|
||||
/* 54: 0x2 BTE Error Response Long */
|
||||
xpcBteSh2RspLong = xpcBteSh2Start + BTEFAIL_SH2_RESP_LONG,
|
||||
|
||||
/* 56: 0x4 BTE Error Response DSB */
|
||||
xpcBteSh2RspDSB = xpcBteSh2Start + BTEFAIL_SH2_RESP_DSP,
|
||||
|
||||
/* 60: 0x8 BTE Error Response Access */
|
||||
xpcBteSh2RspAccess = xpcBteSh2Start + BTEFAIL_SH2_RESP_ACCESS,
|
||||
|
||||
/* 68: 0x10 BTE Error CRB timeout */
|
||||
xpcBteSh2CRBTO = xpcBteSh2Start + BTEFAIL_SH2_CRB_TO,
|
||||
|
||||
/* 84: 0x20 BTE Error NACK limit */
|
||||
xpcBteSh2NACKLimit = xpcBteSh2Start + BTEFAIL_SH2_NACK_LIMIT,
|
||||
|
||||
/* 115: BTE end */
|
||||
xpcBteSh2End = xpcBteSh2Start + BTEFAIL_SH2_ALL,
|
||||
|
||||
xpcUnknownReason /* 116: unknown reason -- must be last in list */
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 2004-2006 Silicon Graphics, Inc. All Rights Reserved.
|
||||
* Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved.
|
||||
*/
|
||||
|
||||
|
||||
|
@ -1211,6 +1211,12 @@ xpc_IPI_init(int index)
|
|||
static inline enum xpc_retval
|
||||
xpc_map_bte_errors(bte_result_t error)
|
||||
{
|
||||
if (is_shub2()) {
|
||||
if (BTE_VALID_SH2_ERROR(error))
|
||||
return xpcBteSh2Start + error;
|
||||
else
|
||||
return xpcBteUnmappedError;
|
||||
}
|
||||
switch (error) {
|
||||
case BTE_SUCCESS: return xpcSuccess;
|
||||
case BTEFAIL_DIR: return xpcBteDirectoryError;
|
||||
|
|
|
@ -92,6 +92,10 @@ void smp_local_flush_tlb(void);
|
|||
#define smp_local_flush_tlb()
|
||||
#endif
|
||||
|
||||
#define flush_tlb_kernel_range(start, end) flush_tlb_all() /* XXX fix me */
|
||||
static inline void flush_tlb_kernel_range(unsigned long start,
|
||||
unsigned long end)
|
||||
{
|
||||
flush_tlb_all(); /* XXX fix me */
|
||||
}
|
||||
|
||||
#endif /* _ASM_IA64_TLBFLUSH_H */
|
||||
|
|
Loading…
Reference in a new issue