KVM: arm/arm64: vgic-new: Add MMIO handling framework
Add an MMIO handling framework to the VGIC emulation: Each register is described by its offset, size (or number of bits per IRQ, if applicable) and the read/write handler functions. We provide initialization macros to describe each GIC register later easily. Separate dispatch functions for read and write accesses are connected to the kvm_io_bus framework and binary-search for the responsible register handler based on the offset address within the region. We convert the incoming data (referenced by a pointer) to the host's endianess and use pass-by-value to hand the data over to the actual handler functions. The register handler prototype and the endianess conversion are courtesy of Christoffer Dall. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>hifive-unleashed-5.1
Marc Zyngier
Christoffer Dall
parent
90eee56c5f
commit
4493b1c486
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@ -106,6 +106,16 @@ struct vgic_irq {
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enum vgic_irq_config config; /* Level or edge */
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};
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struct vgic_register_region;
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struct vgic_io_device {
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gpa_t base_addr;
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struct kvm_vcpu *redist_vcpu;
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const struct vgic_register_region *regions;
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int nr_regions;
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struct kvm_io_device dev;
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};
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struct vgic_dist {
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bool in_kernel;
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bool ready;
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@ -132,6 +142,9 @@ struct vgic_dist {
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bool enabled;
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struct vgic_irq *spis;
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struct vgic_io_device dist_iodev;
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struct vgic_io_device *redist_iodevs;
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};
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struct vgic_v2_cpu_if {
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@ -0,0 +1,184 @@
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/*
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* VGIC MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/bsearch.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return 0;
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}
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unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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return -1UL;
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}
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val)
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{
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/* Ignore */
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}
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static int match_region(const void *key, const void *elt)
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{
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const unsigned int offset = (unsigned long)key;
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const struct vgic_register_region *region = elt;
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if (offset < region->reg_offset)
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return -1;
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if (offset >= region->reg_offset + region->len)
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return 1;
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return 0;
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}
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/* Find the proper register handler entry given a certain address offset. */
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static const struct vgic_register_region *
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vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
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unsigned int offset)
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{
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return bsearch((void *)(uintptr_t)offset, region, nr_regions,
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sizeof(region[0]), match_region);
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}
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/*
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* kvm_mmio_read_buf() returns a value in a format where it can be converted
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* to a byte array and be directly observed as the guest wanted it to appear
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* in memory if it had done the store itself, which is LE for the GIC, as the
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* guest knows the GIC is always LE.
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*
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* We convert this value to the CPUs native format to deal with it as a data
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* value.
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*/
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unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
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{
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unsigned long data = kvm_mmio_read_buf(val, len);
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switch (len) {
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case 1:
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return data;
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case 2:
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return le16_to_cpu(data);
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case 4:
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return le32_to_cpu(data);
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default:
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return le64_to_cpu(data);
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}
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}
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/*
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* kvm_mmio_write_buf() expects a value in a format such that if converted to
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* a byte array it is observed as the guest would see it if it could perform
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* the load directly. Since the GIC is LE, and the guest knows this, the
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* guest expects a value in little endian format.
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*
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* We convert the data value from the CPUs native format to LE so that the
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* value is returned in the proper format.
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*/
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void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
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unsigned long data)
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{
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switch (len) {
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case 1:
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break;
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case 2:
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data = cpu_to_le16(data);
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break;
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case 4:
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data = cpu_to_le32(data);
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break;
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default:
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data = cpu_to_le64(data);
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}
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kvm_mmio_write_buf(buf, len, data);
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}
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static
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struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
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{
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return container_of(dev, struct vgic_io_device, dev);
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}
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static bool check_region(const struct vgic_register_region *region,
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gpa_t addr, int len)
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{
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if ((region->access_flags & VGIC_ACCESS_8bit) && len == 1)
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return true;
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if ((region->access_flags & VGIC_ACCESS_32bit) &&
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len == sizeof(u32) && !(addr & 3))
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return true;
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if ((region->access_flags & VGIC_ACCESS_64bit) &&
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len == sizeof(u64) && !(addr & 7))
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return true;
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return false;
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}
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static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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unsigned long data;
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region || !check_region(region, addr, len)) {
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memset(val, 0, len);
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return 0;
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}
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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data = region->read(r_vcpu, addr, len);
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vgic_data_host_to_mmio_bus(val, len, data);
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return 0;
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}
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static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
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gpa_t addr, int len, const void *val)
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{
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struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
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const struct vgic_register_region *region;
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struct kvm_vcpu *r_vcpu;
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unsigned long data = vgic_data_mmio_bus_to_host(val, len);
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region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
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addr - iodev->base_addr);
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if (!region)
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return 0;
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if (!check_region(region, addr, len))
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return 0;
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r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
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region->write(r_vcpu, addr, len, data);
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return 0;
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}
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struct kvm_io_device_ops kvm_io_gic_ops = {
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.read = dispatch_mmio_read,
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.write = dispatch_mmio_write,
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};
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@ -0,0 +1,99 @@
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/*
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* Copyright (C) 2015, 2016 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __KVM_ARM_VGIC_MMIO_H__
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#define __KVM_ARM_VGIC_MMIO_H__
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struct vgic_register_region {
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unsigned int reg_offset;
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unsigned int len;
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unsigned int bits_per_irq;
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unsigned int access_flags;
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unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len);
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void (*write)(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len,
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unsigned long val);
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};
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extern struct kvm_io_device_ops kvm_io_gic_ops;
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#define VGIC_ACCESS_8bit 1
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#define VGIC_ACCESS_32bit 2
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#define VGIC_ACCESS_64bit 4
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/*
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* Generate a mask that covers the number of bytes required to address
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* up to 1024 interrupts, each represented by <bits> bits. This assumes
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* that <bits> is a power of two.
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*/
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#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1)
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/*
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* (addr & mask) gives us the byte offset for the INT ID, so we want to
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* divide this with 'bytes per irq' to get the INT ID, which is given
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* by '(bits) / 8'. But we do this with fixed-point-arithmetic and
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* take advantage of the fact that division by a fraction equals
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* multiplication with the inverted fraction, and scale up both the
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* numerator and denominator with 8 to support at most 64 bits per IRQ:
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*/
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#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \
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64 / (bits) / 8)
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/*
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* Some VGIC registers store per-IRQ information, with a different number
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* of bits per IRQ. For those registers this macro is used.
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* The _WITH_LENGTH version instantiates registers with a fixed length
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* and is mutually exclusive with the _PER_IRQ version.
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*/
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#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = bpi, \
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.len = bpi * 1024 / 8, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \
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{ \
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.reg_offset = off, \
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.bits_per_irq = 0, \
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.len = length, \
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.access_flags = acc, \
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.read = rd, \
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.write = wr, \
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}
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int kvm_vgic_register_mmio_region(struct kvm *kvm, struct kvm_vcpu *vcpu,
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struct vgic_register_region *reg_desc,
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struct vgic_io_device *region,
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int nr_irqs, bool offset_private);
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unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
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void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
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unsigned long data);
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unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len);
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
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unsigned int len, unsigned long val);
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#endif
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