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Staging/IIO patches for 4.15-rc1 

Here is the "big" staging and IIO driver update for 4.15-rc1.
 
 Lots and lots of little changes, almost all minor code cleanups as the
 Outreachy application process happened during this development cycle.
 Also happened was a lot of IIO driver activity, and the typec USB code
 moving out of staging to drivers/usb (same commits are in the USB tree
 on a persistent branch to not cause merge issues.)
 
 Overall, it's a wash, I think we added a few hundred more lines than
 removed, but really only a few thousand were modified at all.
 
 All of these have been in linux-next for a while.  There might be a
 merge issue with Al's vfs tree in the pi433 driver (take his changes,
 they are always better), and the media tree with some of the odd atomisp
 cleanups (take the media tree's version).
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'staging-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging and IIO updates from Greg KH:
 "Here is the "big" staging and IIO driver update for 4.15-rc1.

  Lots and lots of little changes, almost all minor code cleanups as the
  Outreachy application process happened during this development cycle.
  Also happened was a lot of IIO driver activity, and the typec USB code
  moving out of staging to drivers/usb (same commits are in the USB tree
  on a persistent branch to not cause merge issues.)

  Overall, it's a wash, I think we added a few hundred more lines than
  removed, but really only a few thousand were modified at all.

  All of these have been in linux-next for a while. There might be a
  merge issue with Al's vfs tree in the pi433 driver (take his changes,
  they are always better), and the media tree with some of the odd
  atomisp cleanups (take the media tree's version)"

* tag 'staging-4.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (507 commits)
  staging: lustre: add SPDX identifiers to all lustre files
  staging: greybus: Remove redundant license text
  staging: greybus: add SPDX identifiers to all greybus driver files
  staging: ccree: simplify ioread/iowrite
  staging: ccree: simplify registers access
  staging: ccree: simplify error handling logic
  staging: ccree: remove dead code
  staging: ccree: handle limiting of DMA masks
  staging: ccree: copy IV to DMAable memory
  staging: fbtft: remove redundant initialization of buf
  staging: sm750fb: Fix parameter mistake in poke32
  staging: wilc1000: Fix bssid buffer offset in Txq
  staging: fbtft: fb_ssd1331: fix mirrored display
  staging: android: Fix checkpatch.pl error
  staging: greybus: loopback: convert loopback to use generic async operations
  staging: greybus: operation: add private data with get/set accessors
  staging: greybus: loopback: Fix iteration count on async path
  staging: greybus: loopback: Hold per-connection mutex across operations
  staging: greybus/loopback: use ktime_get() for time intervals
  staging: fsl-dpaa2/eth: Extra headroom in RX buffers
  ...
hifive-unleashed-5.1
Linus Torvalds 2017-11-13 20:53:28 -08:00
parent 3c073991eb c14dd9d5f8
commit 449fcf3ab0
1008 changed files with 8575 additions and 8394 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/ABI/testing/sysfs-bus-iio
View File

@ -522,6 +522,7 @@ Description:
Specifies the output powerdown mode.
DAC output stage is disconnected from the amplifier and
1kohm_to_gnd: connected to ground via an 1kOhm resistor,
2.5kohm_to_gnd: connected to ground via a 2.5kOhm resistor,
6kohm_to_gnd: connected to ground via a 6kOhm resistor,
20kohm_to_gnd: connected to ground via a 20kOhm resistor,
90kohm_to_gnd: connected to ground via a 90kOhm resistor,
@ -1242,9 +1243,9 @@ What: /sys/.../iio:deviceX/in_distance_raw
KernelVersion: 4.0
Contact: linux-iio@vger.kernel.org
Description:
This attribute is used to read the distance covered by the user
since the last reboot while activated. Units after application
of scale are meters.
This attribute is used to read the measured distance to an object
or the distance covered by the user since the last reboot while
activated. Units after application of scale are meters.
What: /sys/bus/iio/devices/iio:deviceX/store_eeprom
KernelVersion: 3.4.0

10
Documentation/ABI/testing/sysfs-bus-iio-cros-ec
View File

@ -16,3 +16,13 @@ Description:
the motion sensor is placed. For example, in a laptop a motion
sensor can be located on the base or on the lid. Current valid
values are 'base' and 'lid'.
What: /sys/bus/iio/devices/iio:deviceX/id
Date: Septembre 2017
KernelVersion: 4.14
Contact: linux-iio@vger.kernel.org
Description:
This attribute is exposed by the CrOS EC legacy accelerometer
driver and represents the sensor ID as exposed by the EC. This
ID is used by the Android sensor service hardware abstraction
layer (sensor HAL) through the Android container on ChromeOS.

14
Documentation/devicetree/bindings/iio/adc/mcp320x.txt
View File

@ -29,15 +29,29 @@ Required properties:
"microchip,mcp3204"
"microchip,mcp3208"
"microchip,mcp3301"
"microchip,mcp3550-50"
"microchip,mcp3550-60"
"microchip,mcp3551"
"microchip,mcp3553"
NOTE: The use of the compatibles with no vendor prefix
is deprecated and only listed because old DT use them.
- spi-cpha, spi-cpol (boolean):
Either SPI mode (0,0) or (1,1) must be used, so specify
none or both of spi-cpha, spi-cpol. The MCP3550/1/3
is more efficient in mode (1,1) as only 3 instead of
4 bytes need to be read from the ADC, but not all SPI
masters support it.
- vref-supply: Phandle to the external reference voltage supply.
Examples:
spi_controller {
mcp3x0x@0 {
compatible = "mcp3002";
reg = <0>;
spi-max-frequency = <1000000>;
vref-supply = <&vref_reg>;
};
};

1
Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt
View File

@ -12,6 +12,7 @@ for the Thermal Controller which holds a phandle to the AUXADC.
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-auxadc": For MT2701 family of SoCs
- "mediatek,mt2712-auxadc": For MT2712 family of SoCs
- "mediatek,mt7622-auxadc": For MT7622 family of SoCs
- "mediatek,mt8173-auxadc": For MT8173 family of SoCs
- reg: Address range of the AUXADC unit.

20
Documentation/devicetree/bindings/iio/dac/ds4424.txt 100644
View File

@ -0,0 +1,20 @@
Maxim Integrated DS4422/DS4424 7-bit Sink/Source Current DAC Device Driver
Datasheet publicly available at:
https://datasheets.maximintegrated.com/en/ds/DS4422-DS4424.pdf
Required properties:
- compatible: Should be one of
maxim,ds4422
maxim,ds4424
- reg: Should contain the DAC I2C address
Optional properties:
- vcc-supply: Power supply is optional. If not defined, driver will ignore it.
Example:
ds4224@10 {
compatible = "maxim,ds4424";
reg = <0x10>; /* When A0, A1 pins are ground */
vcc-supply = <&vcc_3v3>;
};

34
Documentation/devicetree/bindings/iio/dac/ti-dac082s085.txt 100644
View File

@ -0,0 +1,34 @@
Texas Instruments 8/10/12-bit 2/4-channel DAC driver
Required properties:
- compatible: Must be one of:
"ti,dac082s085"
"ti,dac102s085"
"ti,dac122s085"
"ti,dac084s085"
"ti,dac104s085"
"ti,dac124s085"
- reg: Chip select number.
- spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify
either spi-cpha or spi-cpol (but not both).
- vref-supply: Phandle to the external reference voltage supply.
For other required and optional properties of SPI slave nodes please refer to
../../spi/spi-bus.txt.
Example:
vref_2v5_reg: regulator-vref {
compatible = "regulator-fixed";
regulator-name = "2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
dac@0 {
compatible = "ti,dac082s085";
reg = <0>;
spi-max-frequency = <40000000>;
spi-cpol;
vref-supply = <&vref_2v5_reg>;
};

4
Documentation/devicetree/bindings/iio/health/max30100.txt
View File

@ -20,9 +20,9 @@ Optional properties:
Example:
max30100@057 {
max30100@57 {
compatible = "maxim,max30100";
reg = <57>;
reg = <0x57>;
maxim,led-current-microamp = <24000 50000>;
interrupt-parent = <&gpio1>;
interrupts = <16 2>;

2
Documentation/devicetree/bindings/iio/health/max30102.txt
View File

@ -20,7 +20,7 @@ Optional properties:
Example:
max30100@57 {
max30102@57 {
compatible = "maxim,max30102";
reg = <0x57>;
maxim,red-led-current-microamp = <7000>;

4
Documentation/devicetree/bindings/iio/st-sensors.txt
View File

@ -46,6 +46,8 @@ Accelerometers:
- st,h3lis331dl-accel
- st,lng2dm-accel
- st,lis3l02dq
- st,lis2dw12
- st,lis3dhh
Gyroscopes:
- st,l3g4200d-gyro
@ -71,3 +73,5 @@ Pressure sensors:
- st,lps25h-press
- st,lps331ap-press
- st,lps22hb-press
- st,lps33hw
- st,lps35hw

3
arch/arm/configs/pxa_defconfig
View File

@ -219,7 +219,8 @@ CONFIG_AD525X_DPOT_I2C=m
CONFIG_ICS932S401=m
CONFIG_APDS9802ALS=m
CONFIG_ISL29003=m
CONFIG_TI_DAC7512=m
CONFIG_IIO=m
CONFIG_AD5446=m
CONFIG_EEPROM_AT24=m
CONFIG_SENSORS_LIS3_SPI=m
CONFIG_IDE=m

3
arch/arm/configs/raumfeld_defconfig
View File

@ -37,7 +37,8 @@ CONFIG_MTD_NAND_PXA3xx=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_ISL29003=y
CONFIG_TI_DAC7512=y
CONFIG_IIO=y
CONFIG_AD5446=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y

15
drivers/iio/accel/Kconfig
View File

@ -148,6 +148,17 @@ config HID_SENSOR_ACCEL_3D
To compile this driver as a module, choose M here: the
module will be called hid-sensor-accel-3d.
config IIO_CROS_EC_ACCEL_LEGACY
tristate "ChromeOS EC Legacy Accelerometer Sensor"
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
select CROS_EC_LPC_REGISTER_DEVICE
help
Say yes here to get support for accelerometers on Chromebook using
legacy EC firmware.
Sensor data is retrieved through IO memory.
Newer devices should use IIO_CROS_EC_SENSORS.
config IIO_ST_ACCEL_3AXIS
tristate "STMicroelectronics accelerometers 3-Axis Driver"
depends on (I2C || SPI_MASTER) && SYSFS
@ -219,8 +230,8 @@ config KXCJK1013
select IIO_TRIGGERED_BUFFER
help
Say Y here if you want to build a driver for the Kionix KXCJK-1013
triaxial acceleration sensor. This driver also supports KXCJ9-1008
and KXTJ2-1009.
triaxial acceleration sensor. This driver also supports KXCJ9-1008,
KXTJ2-1009 and KXTF9.
To compile this driver as a module, choose M here: the module will
be called kxcjk-1013.

2
drivers/iio/accel/Makefile
View File

@ -44,6 +44,8 @@ obj-$(CONFIG_SCA3000) += sca3000.o
obj-$(CONFIG_STK8312) += stk8312.o
obj-$(CONFIG_STK8BA50) += stk8ba50.o
obj-$(CONFIG_IIO_CROS_EC_ACCEL_LEGACY) += cros_ec_accel_legacy.o
obj-$(CONFIG_IIO_SSP_SENSORS_COMMONS) += ssp_accel_sensor.o
obj-$(CONFIG_IIO_ST_ACCEL_3AXIS) += st_accel.o

1
drivers/iio/accel/adxl345_core.c
View File

@ -95,7 +95,6 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info adxl345_info = {
.driver_module = THIS_MODULE,
.read_raw = adxl345_read_raw,
};

2
drivers/iio/accel/bma180.c
View File

@ -536,7 +536,6 @@ static const struct iio_info bma180_info = {
.attrs = &bma180_attrs_group,
.read_raw = bma180_read_raw,
.write_raw = bma180_write_raw,
.driver_module = THIS_MODULE,
};
static const char * const bma180_power_modes[] = { "low_noise", "low_power" };
@ -700,7 +699,6 @@ static int bma180_trig_try_reen(struct iio_trigger *trig)
static const struct iio_trigger_ops bma180_trigger_ops = {
.set_trigger_state = bma180_data_rdy_trigger_set_state,
.try_reenable = bma180_trig_try_reen,
.owner = THIS_MODULE,
};
static int bma180_probe(struct i2c_client *client,

1
drivers/iio/accel/bma220_spi.c
View File

@ -186,7 +186,6 @@ static int bma220_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info bma220_info = {
.driver_module = THIS_MODULE,
.read_raw = bma220_read_raw,
.write_raw = bma220_write_raw,
.attrs = &bma220_attribute_group,

3
drivers/iio/accel/bmc150-accel-core.c
View File

@ -1094,7 +1094,6 @@ static const struct iio_info bmc150_accel_info = {
.write_event_value = bmc150_accel_write_event,
.write_event_config = bmc150_accel_write_event_config,
.read_event_config = bmc150_accel_read_event_config,
.driver_module = THIS_MODULE,
};
static const struct iio_info bmc150_accel_info_fifo = {
@ -1108,7 +1107,6 @@ static const struct iio_info bmc150_accel_info_fifo = {
.validate_trigger = bmc150_accel_validate_trigger,
.hwfifo_set_watermark = bmc150_accel_set_watermark,
.hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
.driver_module = THIS_MODULE,
};
static const unsigned long bmc150_accel_scan_masks[] = {
@ -1200,7 +1198,6 @@ static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
.set_trigger_state = bmc150_accel_trigger_set_state,
.try_reenable = bmc150_accel_trig_try_reen,
.owner = THIS_MODULE,
};
static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)

423
drivers/iio/accel/cros_ec_accel_legacy.c 100644
View File

@ -0,0 +1,423 @@
/*
* Driver for older Chrome OS EC accelerometer
*
* Copyright 2017 Google, Inc
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* This driver uses the memory mapper cros-ec interface to communicate
* with the Chrome OS EC about accelerometer data.
* Accelerometer access is presented through iio sysfs.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/iio/buffer.h>
#include <linux/iio/iio.h>
#include <linux/iio/kfifo_buf.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/kernel.h>
#include <linux/mfd/cros_ec.h>
#include <linux/mfd/cros_ec_commands.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/platform_device.h>
#define DRV_NAME "cros-ec-accel-legacy"
/*
* Sensor scale hard coded at 10 bits per g, computed as:
* g / (2^10 - 1) = 0.009586168; with g = 9.80665 m.s^-2
*/
#define ACCEL_LEGACY_NSCALE 9586168
/* Indices for EC sensor values. */
enum {
X,
Y,
Z,
MAX_AXIS,
};
/* State data for cros_ec_accel_legacy iio driver. */
struct cros_ec_accel_legacy_state {
struct cros_ec_device *ec;
/*
* Array holding data from a single capture. 2 bytes per channel
* for the 3 channels plus the timestamp which is always last and
* 8-bytes aligned.
*/
s16 capture_data[8];
s8 sign[MAX_AXIS];
u8 sensor_num;
};
static int ec_cmd_read_u8(struct cros_ec_device *ec, unsigned int offset,
u8 *dest)
{
return ec->cmd_readmem(ec, offset, 1, dest);
}
static int ec_cmd_read_u16(struct cros_ec_device *ec, unsigned int offset,
u16 *dest)
{
__le16 tmp;
int ret = ec->cmd_readmem(ec, offset, 2, &tmp);
*dest = le16_to_cpu(tmp);
return ret;
}
/**
* read_ec_until_not_busy() - Read from EC status byte until it reads not busy.
* @st: Pointer to state information for device.
*
* This function reads EC status until its busy bit gets cleared. It does not
* wait indefinitely and returns -EIO if the EC status is still busy after a
* few hundreds milliseconds.
*
* Return: 8-bit status if ok, -EIO on error
*/
static int read_ec_until_not_busy(struct cros_ec_accel_legacy_state *st)
{
struct cros_ec_device *ec = st->ec;
u8 status;
int attempts = 0;
ec_cmd_read_u8(ec, EC_MEMMAP_ACC_STATUS, &status);
while (status & EC_MEMMAP_ACC_STATUS_BUSY_BIT) {
/* Give up after enough attempts, return error. */
if (attempts++ >= 50)
return -EIO;
/* Small delay every so often. */
if (attempts % 5 == 0)
msleep(25);
ec_cmd_read_u8(ec, EC_MEMMAP_ACC_STATUS, &status);
}
return status;
}
/**
* read_ec_accel_data_unsafe() - Read acceleration data from EC shared memory.
* @st: Pointer to state information for device.
* @scan_mask: Bitmap of the sensor indices to scan.
* @data: Location to store data.
*
* This is the unsafe function for reading the EC data. It does not guarantee
* that the EC will not modify the data as it is being read in.
*/
static void read_ec_accel_data_unsafe(struct cros_ec_accel_legacy_state *st,
unsigned long scan_mask, s16 *data)
{
int i = 0;
int num_enabled = bitmap_weight(&scan_mask, MAX_AXIS);
/* Read all sensors enabled in scan_mask. Each value is 2 bytes. */
while (num_enabled--) {
i = find_next_bit(&scan_mask, MAX_AXIS, i);
ec_cmd_read_u16(st->ec,
EC_MEMMAP_ACC_DATA +
sizeof(s16) *
(1 + i + st->sensor_num * MAX_AXIS),
data);
*data *= st->sign[i];
i++;
data++;
}
}
/**
* read_ec_accel_data() - Read acceleration data from EC shared memory.
* @st: Pointer to state information for device.
* @scan_mask: Bitmap of the sensor indices to scan.
* @data: Location to store data.
*
* This is the safe function for reading the EC data. It guarantees that
* the data sampled was not modified by the EC while being read.
*
* Return: 0 if ok, -ve on error
*/
static int read_ec_accel_data(struct cros_ec_accel_legacy_state *st,
unsigned long scan_mask, s16 *data)
{
u8 samp_id = 0xff;
u8 status = 0;
int ret;
int attempts = 0;
/*
* Continually read all data from EC until the status byte after
* all reads reflects that the EC is not busy and the sample id
* matches the sample id from before all reads. This guarantees
* that data read in was not modified by the EC while reading.
*/
while ((status & (EC_MEMMAP_ACC_STATUS_BUSY_BIT |
EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK)) != samp_id) {
/* If we have tried to read too many times, return error. */
if (attempts++ >= 5)
return -EIO;
/* Read status byte until EC is not busy. */
ret = read_ec_until_not_busy(st);
if (ret < 0)
return ret;
status = ret;
/*
* Store the current sample id so that we can compare to the
* sample id after reading the data.
*/
samp_id = status & EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK;
/* Read all EC data, format it, and store it into data. */
read_ec_accel_data_unsafe(st, scan_mask, data);
/* Read status byte. */
ec_cmd_read_u8(st->ec, EC_MEMMAP_ACC_STATUS, &status);
}
return 0;
}
static int cros_ec_accel_legacy_read(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
{
struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev);
s16 data = 0;
int ret = IIO_VAL_INT;
switch (mask) {
case IIO_CHAN_INFO_RAW:
ret = read_ec_accel_data(st, (1 << chan->scan_index), &data);
if (ret)
return ret;
*val = data;
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
*val = 0;
*val2 = ACCEL_LEGACY_NSCALE;
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_CALIBBIAS:
/* Calibration not supported. */
*val = 0;
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
static int cros_ec_accel_legacy_write(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int val, int val2, long mask)
{
/*
* Do nothing but don't return an error code to allow calibration
* script to work.
*/
if (mask == IIO_CHAN_INFO_CALIBBIAS)
return 0;
return -EINVAL;
}
static const struct iio_info cros_ec_accel_legacy_info = {
.read_raw = &cros_ec_accel_legacy_read,
.write_raw = &cros_ec_accel_legacy_write,
};
/**
* cros_ec_accel_legacy_capture() - The trigger handler function
* @irq: The interrupt number.
* @p: Private data - always a pointer to the poll func.
*
* On a trigger event occurring, if the pollfunc is attached then this
* handler is called as a threaded interrupt (and hence may sleep). It
* is responsible for grabbing data from the device and pushing it into
* the associated buffer.
*
* Return: IRQ_HANDLED
*/
static irqreturn_t cros_ec_accel_legacy_capture(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev);
/* Clear capture data. */
memset(st->capture_data, 0, sizeof(st->capture_data));
/*
* Read data based on which channels are enabled in scan mask. Note
* that on a capture we are always reading the calibrated data.
*/
read_ec_accel_data(st, *indio_dev->active_scan_mask, st->capture_data);
iio_push_to_buffers_with_timestamp(indio_dev, (void *)st->capture_data,
iio_get_time_ns(indio_dev));
/*
* Tell the core we are done with this trigger and ready for the
* next one.
*/
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static char *cros_ec_accel_legacy_loc_strings[] = {
[MOTIONSENSE_LOC_BASE] = "base",
[MOTIONSENSE_LOC_LID] = "lid",
[MOTIONSENSE_LOC_MAX] = "unknown",
};
static ssize_t cros_ec_accel_legacy_loc(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev);
return sprintf(buf, "%s\n",
cros_ec_accel_legacy_loc_strings[st->sensor_num +
MOTIONSENSE_LOC_BASE]);
}
static ssize_t cros_ec_accel_legacy_id(struct iio_dev *indio_dev,
uintptr_t private,
const struct iio_chan_spec *chan,
char *buf)
{
struct cros_ec_accel_legacy_state *st = iio_priv(indio_dev);
return sprintf(buf, "%d\n", st->sensor_num);
}
static const struct iio_chan_spec_ext_info cros_ec_accel_legacy_ext_info[] = {
{
.name = "id",
.shared = IIO_SHARED_BY_ALL,
.read = cros_ec_accel_legacy_id,
},
{
.name = "location",
.shared = IIO_SHARED_BY_ALL,
.read = cros_ec_accel_legacy_loc,
},
{ }
};
#define CROS_EC_ACCEL_LEGACY_CHAN(_axis) \
{ \
.type = IIO_ACCEL, \
.channel2 = IIO_MOD_X + (_axis), \
.modified = 1, \
.info_mask_separate = \
BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
.ext_info = cros_ec_accel_legacy_ext_info, \
.scan_type = { \
.sign = 's', \
.realbits = 16, \
.storagebits = 16, \
}, \
} \
static struct iio_chan_spec ec_accel_channels[] = {
CROS_EC_ACCEL_LEGACY_CHAN(X),
CROS_EC_ACCEL_LEGACY_CHAN(Y),
CROS_EC_ACCEL_LEGACY_CHAN(Z),
IIO_CHAN_SOFT_TIMESTAMP(MAX_AXIS)
};
static int cros_ec_accel_legacy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct cros_ec_dev *ec = dev_get_drvdata(dev->parent);
struct cros_ec_sensor_platform *sensor_platform = dev_get_platdata(dev);
struct iio_dev *indio_dev;
struct cros_ec_accel_legacy_state *state;
int ret, i;
if (!ec || !ec->ec_dev) {
dev_warn(&pdev->dev, "No EC device found.\n");
return -EINVAL;
}
if (!ec->ec_dev->cmd_readmem) {
dev_warn(&pdev->dev, "EC does not support direct reads.\n");
return -EINVAL;
}
indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*state));
if (!indio_dev)
return -ENOMEM;
platform_set_drvdata(pdev, indio_dev);
state = iio_priv(indio_dev);
state->ec = ec->ec_dev;
state->sensor_num = sensor_platform->sensor_num;
indio_dev->dev.parent = dev;
indio_dev->name = pdev->name;
indio_dev->channels = ec_accel_channels;
/*
* Present the channel using HTML5 standard:
* need to invert X and Y and invert some lid axis.
*/
for (i = X ; i < MAX_AXIS; i++) {
switch (i) {
case X:
ec_accel_channels[X].scan_index = Y;
case Y:
ec_accel_channels[Y].scan_index = X;
case Z:
ec_accel_channels[Z].scan_index = Z;
}
if (state->sensor_num == MOTIONSENSE_LOC_LID && i != Y)
state->sign[i] = -1;
else
state->sign[i] = 1;
}
indio_dev->num_channels = ARRAY_SIZE(ec_accel_channels);
indio_dev->dev.parent = &pdev->dev;
indio_dev->info = &cros_ec_accel_legacy_info;
indio_dev->modes = INDIO_DIRECT_MODE;
ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
cros_ec_accel_legacy_capture,
NULL);
if (ret)
return ret;
return devm_iio_device_register(dev, indio_dev);
}
static struct platform_driver cros_ec_accel_platform_driver = {
.driver = {
.name = DRV_NAME,
},
.probe = cros_ec_accel_legacy_probe,
};
module_platform_driver(cros_ec_accel_platform_driver);
MODULE_DESCRIPTION("ChromeOS EC legacy accelerometer driver");
MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);

1
drivers/iio/accel/da280.c
View File

@ -88,7 +88,6 @@ static int da280_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info da280_info = {
.driver_module = THIS_MODULE,
.read_raw = da280_read_raw,
};

1
drivers/iio/accel/da311.c
View File

@ -212,7 +212,6 @@ static int da311_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info da311_info = {
.driver_module = THIS_MODULE,
.read_raw = da311_read_raw,
};

1
drivers/iio/accel/dmard06.c
View File

@ -124,7 +124,6 @@ static int dmard06_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info dmard06_info = {
.driver_module = THIS_MODULE,
.read_raw = dmard06_read_raw,
};

1
drivers/iio/accel/dmard09.c
View File

@ -93,7 +93,6 @@ static int dmard09_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info dmard09_info = {
.driver_module = THIS_MODULE,
.read_raw = dmard09_read_raw,
};

1
drivers/iio/accel/dmard10.c
View File

@ -170,7 +170,6 @@ static int dmard10_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info dmard10_info = {
.driver_module = THIS_MODULE,
.read_raw = dmard10_read_raw,
};

1
drivers/iio/accel/hid-sensor-accel-3d.c
View File

@ -225,7 +225,6 @@ static int accel_3d_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info accel_3d_info = {
.driver_module = THIS_MODULE,
.read_raw = &accel_3d_read_raw,
.write_raw = &accel_3d_write_raw,
};

356
drivers/iio/accel/kxcjk-1013.c
View File

@ -34,6 +34,13 @@
#define KXCJK1013_DRV_NAME "kxcjk1013"
#define KXCJK1013_IRQ_NAME "kxcjk1013_event"
#define KXTF9_REG_HP_XOUT_L 0x00
#define KXTF9_REG_HP_XOUT_H 0x01
#define KXTF9_REG_HP_YOUT_L 0x02
#define KXTF9_REG_HP_YOUT_H 0x03
#define KXTF9_REG_HP_ZOUT_L 0x04
#define KXTF9_REG_HP_ZOUT_H 0x05
#define KXCJK1013_REG_XOUT_L 0x06
/*
* From low byte X axis register, all the other addresses of Y and Z can be
@ -48,17 +55,33 @@
#define KXCJK1013_REG_DCST_RESP 0x0C
#define KXCJK1013_REG_WHO_AM_I 0x0F
#define KXCJK1013_REG_INT_SRC1 0x16
#define KXTF9_REG_TILT_POS_CUR 0x10
#define KXTF9_REG_TILT_POS_PREV 0x11
#define KXTF9_REG_INT_SRC1 0x15
#define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */
#define KXCJK1013_REG_INT_SRC2 0x17
#define KXCJK1013_REG_STATUS_REG 0x18
#define KXCJK1013_REG_INT_REL 0x1A
#define KXCJK1013_REG_CTRL1 0x1B
#define KXCJK1013_REG_CTRL2 0x1D
#define KXTF9_REG_CTRL2 0x1C
#define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */
#define KXCJK1013_REG_INT_CTRL1 0x1E
#define KXCJK1013_REG_INT_CTRL2 0x1F
#define KXTF9_REG_INT_CTRL3 0x20
#define KXCJK1013_REG_DATA_CTRL 0x21
#define KXTF9_REG_TILT_TIMER 0x28
#define KXCJK1013_REG_WAKE_TIMER 0x29
#define KXTF9_REG_TDT_TIMER 0x2B
#define KXTF9_REG_TDT_THRESH_H 0x2C
#define KXTF9_REG_TDT_THRESH_L 0x2D
#define KXTF9_REG_TDT_TAP_TIMER 0x2E
#define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
#define KXTF9_REG_TDT_LATENCY_TIMER 0x30
#define KXTF9_REG_TDT_WINDOW_TIMER 0x31
#define KXCJK1013_REG_SELF_TEST 0x3A
#define KXTF9_REG_WAKE_THRESH 0x5A
#define KXTF9_REG_TILT_ANGLE 0x5C
#define KXTF9_REG_HYST_SET 0x5F
#define KXCJK1013_REG_WAKE_THRES 0x6A
#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
@ -67,14 +90,33 @@
#define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
#define KXCJK1013_REG_INT_REG1_BIT_IEA BIT(4)
#define KXCJK1013_REG_INT_REG1_BIT_IEN BIT(5)
#define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
#define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
#define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
#define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
#define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
#define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
#define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
#define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
#define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
#define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
#define KXCJK1013_MAX_STARTUP_TIME_US 100000
#define KXCJK1013_SLEEP_DELAY_MS 2000
#define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
#define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
#define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
#define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
#define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
#define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
#define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
/* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
@ -88,6 +130,7 @@ enum kx_chipset {
KXCJK1013,
KXCJ91008,
KXTJ21009,
KXTF9,
KX_MAX_CHIPS /* this must be last */
};
@ -128,15 +171,42 @@ enum kxcjk1013_range {
KXCJK1013_RANGE_8G,
};
static const struct {
struct kx_odr_map {
int val;
int val2;
int odr_bits;
} samp_freq_table[] = { {0, 781000, 0x08}, {1, 563000, 0x09},
{3, 125000, 0x0A}, {6, 250000, 0x0B}, {12, 500000, 0},
{25, 0, 0x01}, {50, 0, 0x02}, {100, 0, 0x03},
{200, 0, 0x04}, {400, 0, 0x05}, {800, 0, 0x06},
{1600, 0, 0x07} };
int wuf_bits;
};
static const struct kx_odr_map samp_freq_table[] = {
{ 0, 781000, 0x08, 0x00 },
{ 1, 563000, 0x09, 0x01 },
{ 3, 125000, 0x0A, 0x02 },
{ 6, 250000, 0x0B, 0x03 },
{ 12, 500000, 0x00, 0x04 },
{ 25, 0, 0x01, 0x05 },
{ 50, 0, 0x02, 0x06 },
{ 100, 0, 0x03, 0x06 },
{ 200, 0, 0x04, 0x06 },
{ 400, 0, 0x05, 0x06 },
{ 800, 0, 0x06, 0x06 },
{ 1600, 0, 0x07, 0x06 },
};
static const char *const kxcjk1013_samp_freq_avail =
"0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
static const struct kx_odr_map kxtf9_samp_freq_table[] = {
{ 25, 0, 0x01, 0x00 },
{ 50, 0, 0x02, 0x01 },
{ 100, 0, 0x03, 0x01 },
{ 200, 0, 0x04, 0x01 },
{ 400, 0, 0x05, 0x01 },
{ 800, 0, 0x06, 0x01 },
};
static const char *const kxtf9_samp_freq_avail =
"25 50 100 200 400 800";
/* Refer to section 4 of the specification */
static const struct {
@ -188,6 +258,15 @@ static const struct {
{0x06, 3000},
{0x07, 2000},
},
/* KXTF9 */
{
{0x01, 81000},
{0x02, 41000},
{0x03, 21000},
{0x04, 11000},
{0x05, 5100},
{0x06, 2700},
},
};
static const struct {
@ -198,23 +277,6 @@ static const struct {
{19163, 1, 0},
{38326, 0, 1} };
static const struct {
int val;
int val2;
int odr_bits;
} wake_odr_data_rate_table[] = { {0, 781000, 0x00},
{1, 563000, 0x01},
{3, 125000, 0x02},
{6, 250000, 0x03},
{12, 500000, 0x04},
{25, 0, 0x05},
{50, 0, 0x06},
{100, 0, 0x06},
{200, 0, 0x06},
{400, 0, 0x06},
{800, 0, 0x06},
{1600, 0, 0x06} };
static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
enum kxcjk1013_mode mode)
{
@ -341,9 +403,9 @@ static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
}
if (data->active_high_intr)
ret |= KXCJK1013_REG_INT_REG1_BIT_IEA;
ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;
else
ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEA;
ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;
ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
ret);
@ -401,7 +463,7 @@ static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
{
int ret;
int waketh_reg, ret;
ret = i2c_smbus_write_byte_data(data->client,
KXCJK1013_REG_WAKE_TIMER,
@ -412,8 +474,9 @@ static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
return ret;
}
ret = i2c_smbus_write_byte_data(data->client,
KXCJK1013_REG_WAKE_THRES,
waketh_reg = data->chipset == KXTF9 ?
KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES;
ret = i2c_smbus_write_byte_data(data->client, waketh_reg,
data->wake_thres);
if (ret < 0) {
dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
@ -449,9 +512,9 @@ static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
}
if (status)
ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
else
ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
ret);
@ -509,9 +572,9 @@ static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
}
if (status)
ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
else
ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
ret);
@ -547,28 +610,30 @@ static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
return 0;
}
static int kxcjk1013_convert_freq_to_bit(int val, int val2)
static const struct kx_odr_map *kxcjk1013_find_odr_value(
const struct kx_odr_map *map, size_t map_size, int val, int val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
if (samp_freq_table[i].val == val &&
samp_freq_table[i].val2 == val2) {
return samp_freq_table[i].odr_bits;
}
for (i = 0; i < map_size; ++i) {
if (map[i].val == val && map[i].val2 == val2)
return &map[i];
}
return -EINVAL;
return ERR_PTR(-EINVAL);
}
static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2)
static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map,
size_t map_size, int odr_bits,
int *val, int *val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(wake_odr_data_rate_table); ++i) {
if (wake_odr_data_rate_table[i].val == val &&
wake_odr_data_rate_table[i].val2 == val2) {
return wake_odr_data_rate_table[i].odr_bits;
for (i = 0; i < map_size; ++i) {
if (map[i].odr_bits == odr_bits) {
*val = map[i].val;
*val2 = map[i].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
}
@ -578,16 +643,24 @@ static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2)
static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
{
int ret;
int odr_bits;
enum kxcjk1013_mode store_mode;
const struct kx_odr_map *odr_setting;
ret = kxcjk1013_get_mode(data, &store_mode);
if (ret < 0)
return ret;
odr_bits = kxcjk1013_convert_freq_to_bit(val, val2);
if (odr_bits < 0)
return odr_bits;
if (data->chipset == KXTF9)
odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
ARRAY_SIZE(kxtf9_samp_freq_table),
val, val2);
else
odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
ARRAY_SIZE(samp_freq_table),
val, val2);
if (IS_ERR(odr_setting))
return PTR_ERR(odr_setting);
/* To change ODR, the chip must be set to STANDBY as per spec */
ret = kxcjk1013_set_mode(data, STANDBY);
@ -595,20 +668,16 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
return ret;
ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
odr_bits);
odr_setting->odr_bits);
if (ret < 0) {
dev_err(&data->client->dev, "Error writing data_ctrl\n");
return ret;
}
data->odr_bits = odr_bits;
odr_bits = kxcjk1013_convert_wake_odr_to_bit(val, val2);
if (odr_bits < 0)
return odr_bits;
data->odr_bits = odr_setting->odr_bits;
ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
odr_bits);
odr_setting->wuf_bits);
if (ret < 0) {
dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
return ret;
@ -625,17 +694,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
{
int i;
for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
if (samp_freq_table[i].odr_bits == data->odr_bits) {
*val = samp_freq_table[i].val;
*val2 = samp_freq_table[i].val2;
return IIO_VAL_INT_PLUS_MICRO;
}
}
return -EINVAL;
if (data->chipset == KXTF9)
return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
ARRAY_SIZE(kxtf9_samp_freq_table),
data->odr_bits, val, val2);
else
return kxcjk1013_convert_odr_value(samp_freq_table,
ARRAY_SIZE(samp_freq_table),
data->odr_bits, val, val2);
}
static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
@ -886,13 +952,29 @@ static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
return kxcjk1013_set_power_state(data, false);
}
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
"0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600");
static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct kxcjk1013_data *data = iio_priv(indio_dev);
const char *str;
if (data->chipset == KXTF9)
str = kxtf9_samp_freq_avail;
else
str = kxcjk1013_samp_freq_avail;
return sprintf(buf, "%s\n", str);
}
static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
kxcjk1013_get_samp_freq_avail, NULL, 0);
static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
static struct attribute *kxcjk1013_attributes[] = {
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr,
&iio_const_attr_in_accel_scale_available.dev_attr.attr,
NULL,
};
@ -950,7 +1032,6 @@ static const struct iio_info kxcjk1013_info = {
.write_event_value = kxcjk1013_write_event,
.write_event_config = kxcjk1013_write_event_config,
.read_event_config = kxcjk1013_read_event_config,
.driver_module = THIS_MODULE,
};
static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0};
@ -1036,9 +1117,74 @@ static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
.set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
.try_reenable = kxcjk1013_trig_try_reen,
.owner = THIS_MODULE,
};
static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev)
{
struct kxcjk1013_data *data = iio_priv(indio_dev);
int ret = i2c_smbus_read_byte_data(data->client,
KXCJK1013_REG_INT_SRC2);
if (ret < 0) {
dev_err(&data->client->dev, "Error reading reg_int_src2\n");
return;
}
if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
}
static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
{
struct iio_dev *indio_dev = private;
@ -1051,66 +1197,17 @@ static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
goto ack_intr;
}
if (ret & 0x02) {
ret = i2c_smbus_read_byte_data(data->client,
KXCJK1013_REG_INT_SRC2);
if (ret < 0) {
dev_err(&data->client->dev,
"Error reading reg_int_src2\n");
goto ack_intr;
}
if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
if (data->chipset == KXTF9)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
data->timestamp);
if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL,
0,
IIO_MOD_Z,
IIO_MOD_X_AND_Y_AND_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
data->timestamp);
else
kxcjk1013_report_motion_event(indio_dev);
}
ack_intr:
@ -1403,6 +1500,7 @@ static const struct i2c_device_id kxcjk1013_id[] = {
{"kxcjk1013", KXCJK1013},
{"kxcj91008", KXCJ91008},
{"kxtj21009", KXTJ21009},
{"kxtf9", KXTF9},
{"SMO8500", KXCJ91008},
{}
};

1
drivers/iio/accel/kxsd9.c
View File

@ -390,7 +390,6 @@ static const struct iio_info kxsd9_info = {
.read_raw = &kxsd9_read_raw,
.write_raw = &kxsd9_write_raw,
.attrs = &kxsd9_attribute_group,
.driver_module = THIS_MODULE,
};
/* Four channels apart from timestamp, scan mask = 0x0f */

1
drivers/iio/accel/mc3230.c
View File

@ -107,7 +107,6 @@ static int mc3230_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info mc3230_info = {
.driver_module = THIS_MODULE,
.read_raw = mc3230_read_raw,
};

1
drivers/iio/accel/mma7455_core.c
View File

@ -199,7 +199,6 @@ static const struct iio_info mma7455_info = {
.attrs = &mma7455_group,
.read_raw = mma7455_read_raw,
.write_raw = mma7455_write_raw,
.driver_module = THIS_MODULE,
};
#define MMA7455_CHANNEL(axis, idx) { \

1
drivers/iio/accel/mma7660.c
View File

@ -168,7 +168,6 @@ static int mma7660_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info mma7660_info = {
.driver_module = THIS_MODULE,
.read_raw = mma7660_read_raw,
.attrs = &mma7660_attribute_group,
};

383
drivers/iio/accel/mma8452.c
View File

@ -59,7 +59,9 @@
#define MMA8452_FF_MT_THS 0x17
#define MMA8452_FF_MT_THS_MASK 0x7f
#define MMA8452_FF_MT_COUNT 0x18
#define MMA8452_FF_MT_CHAN_SHIFT 3
#define MMA8452_TRANSIENT_CFG 0x1d
#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
#define MMA8452_TRANSIENT_SRC 0x1e
@ -69,6 +71,7 @@
#define MMA8452_TRANSIENT_THS 0x1f
#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
#define MMA8452_TRANSIENT_COUNT 0x20
#define MMA8452_TRANSIENT_CHAN_SHIFT 1
#define MMA8452_CTRL_REG1 0x2a
#define MMA8452_CTRL_ACTIVE BIT(0)
#define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
@ -107,6 +110,51 @@ struct mma8452_data {
const struct mma_chip_info *chip_info;
};
/**
* struct mma8452_event_regs - chip specific data related to events
* @ev_cfg: event config register address
* @ev_cfg_ele: latch bit in event config register
* @ev_cfg_chan_shift: number of the bit to enable events in X
* direction; in event config register
* @ev_src: event source register address
* @ev_ths: event threshold register address
* @ev_ths_mask: mask for the threshold value
* @ev_count: event count (period) register address
*
* Since not all chips supported by the driver support comparing high pass
* filtered data for events (interrupts), different interrupt sources are
* used for different chips and the relevant registers are included here.
*/
struct mma8452_event_regs {
u8 ev_cfg;
u8 ev_cfg_ele;
u8 ev_cfg_chan_shift;
u8 ev_src;
u8 ev_ths;
u8 ev_ths_mask;
u8 ev_count;
};
static const struct mma8452_event_regs ev_regs_accel_falling = {
.ev_cfg = MMA8452_FF_MT_CFG,
.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
.ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
.ev_src = MMA8452_FF_MT_SRC,
.ev_ths = MMA8452_FF_MT_THS,
.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
.ev_count = MMA8452_FF_MT_COUNT
};
static const struct mma8452_event_regs ev_regs_accel_rising = {
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
};
/**
* struct mma_chip_info - chip specific data
* @chip_id: WHO_AM_I register's value
@ -116,40 +164,16 @@ struct mma8452_data {
* @mma_scales: scale factors for converting register values
* to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
* per mode: m/s^2 and micro m/s^2
* @ev_cfg: event config register address
* @ev_cfg_ele: latch bit in event config register
* @ev_cfg_chan_shift: number of the bit to enable events in X
* direction; in event config register
* @ev_src: event source register address
* @ev_src_xe: bit in event source register that indicates
* an event in X direction
* @ev_src_ye: bit in event source register that indicates
* an event in Y direction
* @ev_src_ze: bit in event source register that indicates
* an event in Z direction
* @ev_ths: event threshold register address
* @ev_ths_mask: mask for the threshold value
* @ev_count: event count (period) register address
*
* Since not all chips supported by the driver support comparing high pass
* filtered data for events (interrupts), different interrupt sources are
* used for different chips and the relevant registers are included here.
* @all_events: all events supported by this chip
* @enabled_events: event flags enabled and handled by this driver
*/
struct mma_chip_info {
u8 chip_id;
const struct iio_chan_spec *channels;
int num_channels;
const int mma_scales[3][2];
u8 ev_cfg;
u8 ev_cfg_ele;
u8 ev_cfg_chan_shift;
u8 ev_src;
u8 ev_src_xe;
u8 ev_src_ye;
u8 ev_src_ze;
u8 ev_ths;
u8 ev_ths_mask;
u8 ev_count;
int all_events;
int enabled_events;
};
enum {
@ -394,11 +418,11 @@ static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
}
static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
mma8452_show_scale_avail, NULL, 0);
static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
0444, mma8452_show_hp_cutoff_avail, NULL, 0);
static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
mma8452_show_os_ratio_avail, NULL, 0);
static int mma8452_get_samp_freq_index(struct mma8452_data *data,
@ -602,9 +626,8 @@ static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
{
int val;
const struct mma_chip_info *chip = data->chip_info;
val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
if (val < 0)
return val;
@ -614,29 +637,28 @@ static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
{
int val;
const struct mma_chip_info *chip = data->chip_info;
if ((state && mma8452_freefall_mode_enabled(data)) ||
(!state && !(mma8452_freefall_mode_enabled(data))))
return 0;
val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
if (val < 0)
return val;
if (state) {
val |= BIT(idx_x + chip->ev_cfg_chan_shift);
val |= BIT(idx_y + chip->ev_cfg_chan_shift);
val |= BIT(idx_z + chip->ev_cfg_chan_shift);
val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
val &= ~MMA8452_FF_MT_CFG_OAE;
} else {
val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
val |= MMA8452_FF_MT_CFG_OAE;
}
return mma8452_change_config(data, chip->ev_cfg, val);
return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
}
static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
@ -740,7 +762,37 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
return ret;
}
static int mma8452_read_thresh(struct iio_dev *indio_dev,
static int mma8452_get_event_regs(struct mma8452_data *data,
const struct iio_chan_spec *chan, enum iio_event_direction dir,
const struct mma8452_event_regs **ev_reg)
{
if (!chan)
return -EINVAL;
switch (chan->type) {
case IIO_ACCEL:
switch (dir) {
case IIO_EV_DIR_RISING:
if ((data->chip_info->all_events
& MMA8452_INT_TRANS) &&
(data->chip_info->enabled_events
& MMA8452_INT_TRANS))
*ev_reg = &ev_regs_accel_rising;
else
*ev_reg = &ev_regs_accel_falling;
return 0;
case IIO_EV_DIR_FALLING:
*ev_reg = &ev_regs_accel_falling;
return 0;
default:
return -EINVAL;
}
default:
return -EINVAL;
}
}
static int mma8452_read_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
@ -749,21 +801,24 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
{
struct mma8452_data *data = iio_priv(indio_dev);
int ret, us, power_mode;
const struct mma8452_event_regs *ev_regs;
ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
if (ret)
return ret;
switch (info) {
case IIO_EV_INFO_VALUE:
ret = i2c_smbus_read_byte_data(data->client,
data->chip_info->ev_ths);
ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
if (ret < 0)
return ret;
*val = ret & data->chip_info->ev_ths_mask;
*val = ret & ev_regs->ev_ths_mask;
return IIO_VAL_INT;
case IIO_EV_INFO_PERIOD:
ret = i2c_smbus_read_byte_data(data->client,
data->chip_info->ev_count);
ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
if (ret < 0)
return ret;
@ -800,7 +855,7 @@ static int mma8452_read_thresh(struct iio_dev *indio_dev,
}
}
static int mma8452_write_thresh(struct iio_dev *indio_dev,
static int mma8452_write_event_value(struct iio_dev *indio_dev,
const struct iio_chan_spec *chan,
enum iio_event_type type,
enum iio_event_direction dir,
@ -809,14 +864,18 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
{
struct mma8452_data *data = iio_priv(indio_dev);
int ret, reg, steps;
const struct mma8452_event_regs *ev_regs;
ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
if (ret)
return ret;
switch (info) {
case IIO_EV_INFO_VALUE:
if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
if (val < 0 || val > ev_regs->ev_ths_mask)
return -EINVAL;
return mma8452_change_config(data, data->chip_info->ev_ths,
val);
return mma8452_change_config(data, ev_regs->ev_ths, val);
case IIO_EV_INFO_PERIOD:
ret = mma8452_get_power_mode(data);
@ -830,8 +889,7 @@ static int mma8452_write_thresh(struct iio_dev *indio_dev,
if (steps < 0 || steps > 0xff)
return -EINVAL;
return mma8452_change_config(data, data->chip_info->ev_count,
steps);
return mma8452_change_config(data, ev_regs->ev_count, steps);
case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
reg = i2c_smbus_read_byte_data(data->client,
@ -861,23 +919,24 @@ static int mma8452_read_event_config(struct iio_dev *indio_dev,
enum iio_event_direction dir)
{
struct mma8452_data *data = iio_priv(indio_dev);
const struct mma_chip_info *chip = data->chip_info;
int ret;
const struct mma8452_event_regs *ev_regs;
ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
if (ret)
return ret;
switch (dir) {
case IIO_EV_DIR_FALLING:
return mma8452_freefall_mode_enabled(data);
case IIO_EV_DIR_RISING:
if (mma8452_freefall_mode_enabled(data))
return 0;
ret = i2c_smbus_read_byte_data(data->client,
data->chip_info->ev_cfg);
ev_regs->ev_cfg);
if (ret < 0)
return ret;
return !!(ret & BIT(chan->scan_index +
chip->ev_cfg_chan_shift));
ev_regs->ev_cfg_chan_shift));
default:
return -EINVAL;
}
@ -890,8 +949,12 @@ static int mma8452_write_event_config(struct iio_dev *indio_dev,
int state)
{
struct mma8452_data *data = iio_priv(indio_dev);
const struct mma_chip_info *chip = data->chip_info;
int val, ret;
const struct mma8452_event_regs *ev_regs;
ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
if (ret)
return ret;
ret = mma8452_set_runtime_pm_state(data->client, state);
if (ret)
@ -901,28 +964,30 @@ static int mma8452_write_event_config(struct iio_dev *indio_dev,
case IIO_EV_DIR_FALLING:
return mma8452_set_freefall_mode(data, state);
case IIO_EV_DIR_RISING:
val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
if (val < 0)
return val;
if (state) {
if (mma8452_freefall_mode_enabled(data)) {
val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
val |= MMA8452_FF_MT_CFG_OAE;
}
val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
val |= BIT(chan->scan_index +
ev_regs->ev_cfg_chan_shift);
} else {
if (mma8452_freefall_mode_enabled(data))
return 0;
val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
val &= ~BIT(chan->scan_index +
ev_regs->ev_cfg_chan_shift);
}
val |= chip->ev_cfg_ele;
val |= ev_regs->ev_cfg_ele;
return mma8452_change_config(data, chip->ev_cfg, val);
return mma8452_change_config(data, ev_regs->ev_cfg, val);
default:
return -EINVAL;
}
@ -934,35 +999,25 @@ static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
s64 ts = iio_get_time_ns(indio_dev);
int src;
src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
if (src < 0)
return;
if (mma8452_freefall_mode_enabled(data)) {
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
IIO_MOD_X_AND_Y_AND_Z,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_FALLING),
ts);
return;
}
if (src & data->chip_info->ev_src_xe)
if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
ts);
if (src & data->chip_info->ev_src_ye)
if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
ts);
if (src & data->chip_info->ev_src_ze)
if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
IIO_EV_TYPE_MAG,
@ -974,7 +1029,6 @@ static irqreturn_t mma8452_interrupt(int irq, void *p)
{
struct iio_dev *indio_dev = p;
struct mma8452_data *data = iio_priv(indio_dev);
const struct mma_chip_info *chip = data->chip_info;
int ret = IRQ_NONE;
int src;
@ -982,15 +1036,29 @@ static irqreturn_t mma8452_interrupt(int irq, void *p)
if (src < 0)
return IRQ_NONE;
if (!(src & data->chip_info->enabled_events))
return IRQ_NONE;
if (src & MMA8452_INT_DRDY) {
iio_trigger_poll_chained(indio_dev->trig);
ret = IRQ_HANDLED;
}
if ((src & MMA8452_INT_TRANS &&
chip->ev_src == MMA8452_TRANSIENT_SRC) ||
(src & MMA8452_INT_FF_MT &&
chip->ev_src == MMA8452_FF_MT_SRC)) {
if (src & MMA8452_INT_FF_MT) {
if (mma8452_freefall_mode_enabled(data)) {
s64 ts = iio_get_time_ns(indio_dev);
iio_push_event(indio_dev,
IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
IIO_MOD_X_AND_Y_AND_Z,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_FALLING),
ts);
}
ret = IRQ_HANDLED;
}
if (src & MMA8452_INT_TRANS) {
mma8452_transient_interrupt(indio_dev);
ret = IRQ_HANDLED;
}
@ -1020,8 +1088,8 @@ done:
}
static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
unsigned reg, unsigned writeval,
unsigned *readval)
unsigned int reg, unsigned int writeval,
unsigned int *readval)
{
int ret;
struct mma8452_data *data = iio_priv(indio_dev);
@ -1222,96 +1290,87 @@ static const struct mma_chip_info mma_chip_info_table[] = {
* g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
*/
.mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = 1,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
.ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
.ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
},
[mma8452] = {
.chip_id = MMA8452_DEVICE_ID,
.channels = mma8452_channels,
.num_channels = ARRAY_SIZE(mma8452_channels),
.mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = 1,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
.ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
.ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
},
[mma8453] = {
.chip_id = MMA8453_DEVICE_ID,
.channels = mma8453_channels,
.num_channels = ARRAY_SIZE(mma8453_channels),
.mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = 1,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
.ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
.ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
},
[mma8652] = {
.chip_id = MMA8652_DEVICE_ID,
.channels = mma8652_channels,
.num_channels = ARRAY_SIZE(mma8652_channels),
.mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
.ev_cfg = MMA8452_FF_MT_CFG,
.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
.ev_cfg_chan_shift = 3,
.ev_src = MMA8452_FF_MT_SRC,
.ev_src_xe = MMA8452_FF_MT_SRC_XHE,
.ev_src_ye = MMA8452_FF_MT_SRC_YHE,
.ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
.ev_ths = MMA8452_FF_MT_THS,
.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
.ev_count = MMA8452_FF_MT_COUNT,
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_FF_MT,
},
[mma8653] = {
.chip_id = MMA8653_DEVICE_ID,
.channels = mma8653_channels,
.num_channels = ARRAY_SIZE(mma8653_channels),
.mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
.ev_cfg = MMA8452_FF_MT_CFG,
.ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
.ev_cfg_chan_shift = 3,
.ev_src = MMA8452_FF_MT_SRC,
.ev_src_xe = MMA8452_FF_MT_SRC_XHE,
.ev_src_ye = MMA8452_FF_MT_SRC_YHE,
.ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
.ev_ths = MMA8452_FF_MT_THS,
.ev_ths_mask = MMA8452_FF_MT_THS_MASK,
.ev_count = MMA8452_FF_MT_COUNT,
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_FF_MT,
},
[fxls8471] = {
.chip_id = FXLS8471_DEVICE_ID,
.channels = mma8451_channels,
.num_channels = ARRAY_SIZE(mma8451_channels),
.mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
.ev_cfg = MMA8452_TRANSIENT_CFG,
.ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
.ev_cfg_chan_shift = 1,
.ev_src = MMA8452_TRANSIENT_SRC,
.ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
.ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
.ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
.ev_ths = MMA8452_TRANSIENT_THS,
.ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
.ev_count = MMA8452_TRANSIENT_COUNT,
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
.all_events = MMA8452_INT_DRDY |
MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
.enabled_events = MMA8452_INT_TRANS |
MMA8452_INT_FF_MT,
},
};
@ -1332,12 +1391,11 @@ static const struct iio_info mma8452_info = {
.read_raw = &mma8452_read_raw,
.write_raw = &mma8452_write_raw,
.event_attrs = &mma8452_event_attribute_group,
.read_event_value = &mma8452_read_thresh,
.write_event_value = &mma8452_write_thresh,
.read_event_value = &mma8452_read_event_value,
.write_event_value = &mma8452_write_event_value,
.read_event_config = &mma8452_read_event_config,
.write_event_config = &mma8452_write_event_config,
.debugfs_reg_access = &mma8452_reg_access_dbg,
.driver_module = THIS_MODULE,
};
static const unsigned long mma8452_scan_masks[] = {0x7, 0};
@ -1368,7 +1426,6 @@ static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
static const struct iio_trigger_ops mma8452_trigger_ops = {
.set_trigger_state = mma8452_data_rdy_trigger_set_state,
.validate_device = iio_trigger_validate_own_device,
.owner = THIS_MODULE,
};
static int mma8452_trigger_setup(struct iio_dev *indio_dev)
@ -1509,16 +1566,6 @@ static int mma8452_probe(struct i2c_client *client,
return ret;
if (client->irq) {
/*
* Although we enable the interrupt sources once and for
* all here the event detection itself is not enabled until
* userspace asks for it by mma8452_write_event_config()
*/
int supported_interrupts = MMA8452_INT_DRDY |
MMA8452_INT_TRANS |
MMA8452_INT_FF_MT;
int enabled_interrupts = MMA8452_INT_TRANS |
MMA8452_INT_FF_MT;
int irq2;
irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
@ -1527,8 +1574,8 @@ static int mma8452_probe(struct i2c_client *client,
dev_dbg(&client->dev, "using interrupt line INT2\n");
} else {
ret = i2c_smbus_write_byte_data(client,
MMA8452_CTRL_REG5,
supported_interrupts);
MMA8452_CTRL_REG5,
data->chip_info->all_events);
if (ret < 0)
return ret;
@ -1536,8 +1583,8 @@ static int mma8452_probe(struct i2c_client *client,
}
ret = i2c_smbus_write_byte_data(client,
MMA8452_CTRL_REG4,
enabled_interrupts);
MMA8452_CTRL_REG4,
data->chip_info->enabled_events);
if (ret < 0)
return ret;

1
drivers/iio/accel/mma9551.c
View File

@ -332,7 +332,6 @@ static const struct iio_chan_spec mma9551_channels[] = {
};
static const struct iio_info mma9551_info = {
.driver_module = THIS_MODULE,
.read_raw = mma9551_read_raw,
.read_event_config = mma9551_read_event_config,
.write_event_config = mma9551_write_event_config,

1
drivers/iio/accel/mma9553.c
View File

@ -987,7 +987,6 @@ static const struct iio_chan_spec mma9553_channels[] = {
};
static const struct iio_info mma9553_info = {
.driver_module = THIS_MODULE,
.read_raw = mma9553_read_raw,
.write_raw = mma9553_write_raw,
.read_event_config = mma9553_read_event_config,

2
drivers/iio/accel/mxc4005.c
View File

@ -264,7 +264,6 @@ static int mxc4005_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info mxc4005_info = {
.driver_module = THIS_MODULE,
.read_raw = mxc4005_read_raw,
.write_raw = mxc4005_write_raw,
.attrs = &mxc4005_attrs_group,
@ -376,7 +375,6 @@ static int mxc4005_trigger_try_reen(struct iio_trigger *trig)
static const struct iio_trigger_ops mxc4005_trigger_ops = {
.set_trigger_state = mxc4005_set_trigger_state,
.try_reenable = mxc4005_trigger_try_reen,
.owner = THIS_MODULE,
};
static int mxc4005_chip_init(struct mxc4005_data *data)

1
drivers/iio/accel/mxc6255.c
View File

@ -78,7 +78,6 @@ static int mxc6255_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info mxc6255_info = {
.driver_module = THIS_MODULE,
.read_raw = mxc6255_read_raw,
};

1
drivers/iio/accel/sca3000.c
View File

@ -1454,7 +1454,6 @@ static const struct iio_info sca3000_info = {
.write_event_value = &sca3000_write_event_value,
.read_event_config = &sca3000_read_event_config,
.write_event_config = &sca3000_write_event_config,
.driver_module = THIS_MODULE,
};
static int sca3000_probe(struct spi_device *spi)

4
drivers/iio/accel/st_accel.h
View File

@ -32,6 +32,8 @@ enum st_accel_type {
H3LIS331DL,
LIS331DL,
LIS3LV02DL,
LIS2DW12,
LIS3DHH,
ST_ACCEL_MAX,
};
@ -52,6 +54,8 @@ enum st_accel_type {
#define LIS2DH12_ACCEL_DEV_NAME "lis2dh12_accel"
#define LIS3L02DQ_ACCEL_DEV_NAME "lis3l02dq"
#define LNG2DM_ACCEL_DEV_NAME "lng2dm"
#define LIS2DW12_ACCEL_DEV_NAME "lis2dw12"
#define LIS3DHH_ACCEL_DEV_NAME "lis3dhh"
/**
* struct st_sensors_platform_data - default accel platform data

248
drivers/iio/accel/st_accel_core.c
View File

@ -159,12 +159,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.mask = 0x80,
},
.drdy_irq = {
.addr = 0x22,
.mask_int1 = 0x10,
.mask_int2 = 0x00,
.int1 = {
.addr = 0x22,
.mask = 0x10,
},
.addr_ihl = 0x25,
.mask_ihl = 0x02,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x23,
@ -229,14 +233,24 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.mask = 0x80,
},
.drdy_irq = {
.addr = 0x22,
.mask_int1 = 0x02,
.mask_int2 = 0x10,
.int1 = {
.addr = 0x22,
.mask = 0x02,
.addr_od = 0x22,
.mask_od = 0x40,
},
.int2 = {
.addr = 0x22,
.mask = 0x10,
.addr_od = 0x22,
.mask_od = 0x40,
},
.addr_ihl = 0x22,
.mask_ihl = 0x80,
.addr_od = 0x22,
.mask_od = 0x40,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x23,
@ -313,12 +327,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.mask = 0x08,
},
.drdy_irq = {
.addr = 0x23,
.mask_int1 = 0x80,
.mask_int2 = 0x00,
.int1 = {
.addr = 0x23,
.mask = 0x80,
},
.addr_ihl = 0x23,
.mask_ihl = 0x40,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
.ig1 = {
.en_addr = 0x23,
.en_mask = 0x08,
@ -387,9 +405,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.mask = 0x01,
},
.drdy_irq = {
.addr = 0x21,
.mask_int1 = 0x04,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.int1 = {
.addr = 0x21,
.mask = 0x04,
},
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x21,
@ -444,14 +467,24 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
},
},
.drdy_irq = {
.addr = 0x22,
.mask_int1 = 0x04,
.mask_int2 = 0x20,
.int1 = {
.addr = 0x22,
.mask = 0x04,
.addr_od = 0x22,
.mask_od = 0x40,
},
.int2 = {
.addr = 0x22,
.mask = 0x20,
.addr_od = 0x22,
.mask_od = 0x40,
},
.addr_ihl = 0x22,
.mask_ihl = 0x80,
.addr_od = 0x22,
.mask_od = 0x40,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x21,
@ -513,9 +546,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.mask = 0x80,
},
.drdy_irq = {
.addr = 0x22,
.mask_int1 = 0x02,
.mask_int2 = 0x10,
.int1 = {
.addr = 0x22,
.mask = 0x02,
},
.int2 = {
.addr = 0x22,
.mask = 0x10,
},
.addr_ihl = 0x22,
.mask_ihl = 0x80,
},
@ -567,9 +605,14 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.bdu = {
},
.drdy_irq = {
.addr = 0x21,
.mask_int1 = 0x04,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.int1 = {
.addr = 0x21,
.mask = 0x04,
},
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x21,
@ -635,12 +678,16 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
},
},
.drdy_irq = {
.addr = 0x22,
.mask_int1 = 0x10,
.mask_int2 = 0x00,
.int1 = {
.addr = 0x22,
.mask = 0x10,
},
.addr_ihl = 0x25,
.mask_ihl = 0x02,
.addr_stat_drdy = ST_SENSORS_DEFAULT_STAT_ADDR,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.sim = {
.addr = 0x23,
@ -649,6 +696,139 @@ static const struct st_sensor_settings st_accel_sensors_settings[] = {
.multi_read_bit = true,
.bootime = 2,
},
{
.wai = 0x44,
.wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
.sensors_supported = {
[0] = LIS2DW12_ACCEL_DEV_NAME,
},
.ch = (struct iio_chan_spec *)st_accel_12bit_channels,
.odr = {
.addr = 0x20,
.mask = 0xf0,
.odr_avl = {
{ .hz = 1, .value = 0x01, },
{ .hz = 12, .value = 0x02, },
{ .hz = 25, .value = 0x03, },
{ .hz = 50, .value = 0x04, },
{ .hz = 100, .value = 0x05, },
{ .hz = 200, .value = 0x06, },
},
},
.pw = {
.addr = 0x20,
.mask = 0xf0,
.value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
},
.fs = {
.addr = 0x25,
.mask = 0x30,
.fs_avl = {
[0] = {
.num = ST_ACCEL_FS_AVL_2G,
.value = 0x00,
.gain = IIO_G_TO_M_S_2(976),
},
[1] = {
.num = ST_ACCEL_FS_AVL_4G,
.value = 0x01,
.gain = IIO_G_TO_M_S_2(1952),
},
[2] = {
.num = ST_ACCEL_FS_AVL_8G,
.value = 0x02,
.gain = IIO_G_TO_M_S_2(3904),
},
[3] = {
.num = ST_ACCEL_FS_AVL_16G,
.value = 0x03,
.gain = IIO_G_TO_M_S_2(7808),
},
},
},
.bdu = {
.addr = 0x21,
.mask = 0x08,
},
.drdy_irq = {
.int1 = {
.addr = 0x23,
.mask = 0x01,
.addr_od = 0x22,
.mask_od = 0x20,
},
.int2 = {
.addr = 0x24,
.mask = 0x01,
.addr_od = 0x22,
.mask_od = 0x20,
},
.addr_ihl = 0x22,
.mask_ihl = 0x08,
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x01,
},
},
.sim = {
.addr = 0x21,
.value = BIT(0),
},
.multi_read_bit = false,
.bootime = 2,
},
{
.wai = 0x11,
.wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
.sensors_supported = {
[0] = LIS3DHH_ACCEL_DEV_NAME,
},
.ch = (struct iio_chan_spec *)st_accel_16bit_channels,
.odr = {
/* just ODR = 1100Hz available */
.odr_avl = {
{ .hz = 1100, .value = 0x00, },
},
},
.pw = {
.addr = 0x20,
.mask = 0x80,
.value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
.value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
},
.fs = {
.fs_avl = {
[0] = {
.num = ST_ACCEL_FS_AVL_2G,
.gain = IIO_G_TO_M_S_2(76),
},
},
},
.bdu = {
.addr = 0x20,
.mask = 0x01,
},
.drdy_irq = {
.int1 = {
.addr = 0x21,
.mask = 0x80,
.addr_od = 0x23,
.mask_od = 0x04,
},
.int2 = {
.addr = 0x22,
.mask = 0x80,
.addr_od = 0x23,
.mask_od = 0x08,
},
.stat_drdy = {
.addr = ST_SENSORS_DEFAULT_STAT_ADDR,
.mask = 0x07,
},
},
.multi_read_bit = false,
.bootime = 2,
},
};
static int st_accel_read_raw(struct iio_dev *indio_dev,
@ -721,7 +901,6 @@ static const struct attribute_group st_accel_attribute_group = {
};
static const struct iio_info accel_info = {
.driver_module = THIS_MODULE,
.attrs = &st_accel_attribute_group,
.read_raw = &st_accel_read_raw,
.write_raw = &st_accel_write_raw,
@ -730,7 +909,6 @@ static const struct iio_info accel_info = {
#ifdef CONFIG_IIO_TRIGGER
static const struct iio_trigger_ops st_accel_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE,
.validate_device = st_sensors_validate_device,
};

5
drivers/iio/accel/st_accel_i2c.c
View File

@ -94,6 +94,10 @@ static const struct of_device_id st_accel_of_match[] = {
.compatible = "st,lng2dm-accel",
.data = LNG2DM_ACCEL_DEV_NAME,
},
{
.compatible = "st,lis2dw12",
.data = LIS2DW12_ACCEL_DEV_NAME,
},
{},
};
MODULE_DEVICE_TABLE(of, st_accel_of_match);
@ -129,6 +133,7 @@ static const struct i2c_device_id st_accel_id_table[] = {
{ H3LIS331DL_ACCEL_DEV_NAME, H3LIS331DL },
{ LIS331DL_ACCEL_DEV_NAME, LIS331DL },
{ LIS3LV02DL_ACCEL_DEV_NAME, LIS3LV02DL },
{ LIS2DW12_ACCEL_DEV_NAME, LIS2DW12 },
{},
};
MODULE_DEVICE_TABLE(i2c, st_accel_id_table);

10
drivers/iio/accel/st_accel_spi.c
View File

@ -82,6 +82,14 @@ static const struct of_device_id st_accel_of_match[] = {
.compatible = "st,lis331dl-accel",
.data = LIS331DL_ACCEL_DEV_NAME,
},
{
.compatible = "st,lis2dw12",
.data = LIS2DW12_ACCEL_DEV_NAME,
},
{
.compatible = "st,lis3dhh",
.data = LIS3DHH_ACCEL_DEV_NAME,
},
{}
};
MODULE_DEVICE_TABLE(of, st_accel_of_match);
@ -133,6 +141,8 @@ static const struct spi_device_id st_accel_id_table[] = {
{ H3LIS331DL_ACCEL_DEV_NAME },
{ LIS331DL_ACCEL_DEV_NAME },
{ LIS3LV02DL_ACCEL_DEV_NAME },
{ LIS2DW12_ACCEL_DEV_NAME },
{ LIS3DHH_ACCEL_DEV_NAME },
{},
};
MODULE_DEVICE_TABLE(spi, st_accel_id_table);

2
drivers/iio/accel/stk8312.c
View File

@ -237,7 +237,6 @@ static int stk8312_data_rdy_trigger_set_state(struct iio_trigger *trig,
static const struct iio_trigger_ops stk8312_trigger_ops = {
.set_trigger_state = stk8312_data_rdy_trigger_set_state,
.owner = THIS_MODULE,
};
static int stk8312_set_sample_rate(struct stk8312_data *data, u8 rate)
@ -421,7 +420,6 @@ static int stk8312_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info stk8312_info = {
.driver_module = THIS_MODULE,
.read_raw = stk8312_read_raw,
.write_raw = stk8312_write_raw,
.attrs = &stk8312_attribute_group,

2
drivers/iio/accel/stk8ba50.c
View File

@ -179,7 +179,6 @@ static int stk8ba50_data_rdy_trigger_set_state(struct iio_trigger *trig,
static const struct iio_trigger_ops stk8ba50_trigger_ops = {
.set_trigger_state = stk8ba50_data_rdy_trigger_set_state,
.owner = THIS_MODULE,
};
static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode)
@ -307,7 +306,6 @@ static int stk8ba50_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info stk8ba50_info = {
.driver_module = THIS_MODULE,
.read_raw = stk8ba50_read_raw,
.write_raw = stk8ba50_write_raw,
.attrs = &stk8ba50_attribute_group,

7
drivers/iio/adc/Kconfig
View File

@ -477,12 +477,13 @@ config MAX9611
called max9611.
config MCP320X
tristate "Microchip Technology MCP3x01/02/04/08"
tristate "Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3"
depends on SPI
help
Say yes here to build support for Microchip Technology's
MCP3001, MCP3002, MCP3004, MCP3008, MCP3201, MCP3202, MCP3204,
MCP3208 or MCP3301 analog to digital converter.
MCP3208, MCP3301, MCP3550, MCP3551 and MCP3553 analog to digital
converters.
This driver can also be built as a module. If so, the module will be
called mcp320x.
@ -595,7 +596,7 @@ config QCOM_SPMI_VADC
config RCAR_GYRO_ADC
tristate "Renesas R-Car GyroADC driver"
depends on ARCH_RCAR_GEN2 || (ARM && COMPILE_TEST)
depends on ARCH_RCAR_GEN2 || COMPILE_TEST
help
Say yes here to build support for the GyroADC found in Renesas
R-Car Gen2 SoCs. This block is a simple SPI offload engine for

1
drivers/iio/adc/ad7266.c
View File

@ -280,7 +280,6 @@ static AD7266_DECLARE_DIFF_CHANNELS_FIXED(u, 'u');
static const struct iio_info ad7266_info = {
.read_raw = &ad7266_read_raw,
.update_scan_mode = &ad7266_update_scan_mode,
.driver_module = THIS_MODULE,
};
static const unsigned long ad7266_available_scan_masks[] = {

1
drivers/iio/adc/ad7291.c
View File

@ -461,7 +461,6 @@ static const struct iio_info ad7291_info = {
.write_event_config = &ad7291_write_event_config,
.read_event_value = &ad7291_read_event_value,
.write_event_value = &ad7291_write_event_value,
.driver_module = THIS_MODULE,
};
static int ad7291_probe(struct i2c_client *client,

1
drivers/iio/adc/ad7298.c
View File

@ -280,7 +280,6 @@ static int ad7298_read_raw(struct iio_dev *indio_dev,
static const struct iio_info ad7298_info = {
.read_raw = &ad7298_read_raw,
.update_scan_mode = ad7298_update_scan_mode,
.driver_module = THIS_MODULE,
};
static int ad7298_probe(struct spi_device *spi)

1
drivers/iio/adc/ad7476.c
View File

@ -195,7 +195,6 @@ static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
};
static const struct iio_info ad7476_info = {
.driver_module = THIS_MODULE,
.read_raw = &ad7476_read_raw,
};

2
drivers/iio/adc/ad7766.c
View File

@ -185,7 +185,6 @@ static const struct iio_buffer_setup_ops ad7766_buffer_setup_ops = {
};
static const struct iio_info ad7766_info = {
.driver_module = THIS_MODULE,
.read_raw = &ad7766_read_raw,
};
@ -208,7 +207,6 @@ static int ad7766_set_trigger_state(struct iio_trigger *trig, bool enable)
}
static const struct iio_trigger_ops ad7766_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = ad7766_set_trigger_state,
.validate_device = iio_trigger_validate_own_device,
};

2
drivers/iio/adc/ad7791.c
View File

@ -308,13 +308,11 @@ static const struct iio_info ad7791_info = {
.read_raw = &ad7791_read_raw,
.attrs = &ad7791_attribute_group,
.validate_trigger = ad_sd_validate_trigger,
.driver_module = THIS_MODULE,
};
static const struct iio_info ad7791_no_filter_info = {
.read_raw = &ad7791_read_raw,
.validate_trigger = ad_sd_validate_trigger,
.driver_module = THIS_MODULE,
};
static int ad7791_setup(struct ad7791_state *st,

2
drivers/iio/adc/ad7793.c
View File

@ -563,7 +563,6 @@ static const struct iio_info ad7793_info = {
.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
.attrs = &ad7793_attribute_group,
.validate_trigger = ad_sd_validate_trigger,
.driver_module = THIS_MODULE,
};
static const struct iio_info ad7797_info = {
@ -572,7 +571,6 @@ static const struct iio_info ad7797_info = {
.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
.attrs = &ad7793_attribute_group,
.validate_trigger = ad_sd_validate_trigger,
.driver_module = THIS_MODULE,
};
#define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \

1
drivers/iio/adc/ad7887.c
View File

@ -229,7 +229,6 @@ static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
static const struct iio_info ad7887_info = {
.read_raw = &ad7887_read_raw,
.driver_module = THIS_MODULE,
};
static int ad7887_probe(struct spi_device *spi)

1
drivers/iio/adc/ad7923.c
View File

@ -262,7 +262,6 @@ static int ad7923_read_raw(struct iio_dev *indio_dev,
static const struct iio_info ad7923_info = {
.read_raw = &ad7923_read_raw,
.update_scan_mode = ad7923_update_scan_mode,
.driver_module = THIS_MODULE,
};
static int ad7923_probe(struct spi_device *spi)

3
drivers/iio/adc/ad799x.c
View File

@ -526,13 +526,11 @@ static const struct attribute_group ad799x_event_attrs_group = {
static const struct iio_info ad7991_info = {
.read_raw = &ad799x_read_raw,
.driver_module = THIS_MODULE,
.update_scan_mode = ad799x_update_scan_mode,
};
static const struct iio_info ad7993_4_7_8_noirq_info = {
.read_raw = &ad799x_read_raw,
.driver_module = THIS_MODULE,
.update_scan_mode = ad799x_update_scan_mode,
};
@ -543,7 +541,6 @@ static const struct iio_info ad7993_4_7_8_irq_info = {
.write_event_config = &ad799x_write_event_config,
.read_event_value = &ad799x_read_event_value,
.write_event_value = &ad799x_write_event_value,
.driver_module = THIS_MODULE,
.update_scan_mode = ad799x_update_scan_mode,
};

1
drivers/iio/adc/ad_sigma_delta.c
View File

@ -463,7 +463,6 @@ int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig)
EXPORT_SYMBOL_GPL(ad_sd_validate_trigger);
static const struct iio_trigger_ops ad_sd_trigger_ops = {
.owner = THIS_MODULE,
};
static int ad_sd_probe_trigger(struct iio_dev *indio_dev)

1
drivers/iio/adc/aspeed_adc.c
View File

@ -165,7 +165,6 @@ static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
}
static const struct iio_info aspeed_adc_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = aspeed_adc_read_raw,
.write_raw = aspeed_adc_write_raw,
.debugfs_reg_access = aspeed_adc_reg_access,

2
drivers/iio/adc/at91-sama5d2_adc.c
View File

@ -348,7 +348,6 @@ static int at91_adc_reenable_trigger(struct iio_trigger *trig)
}
static const struct iio_trigger_ops at91_adc_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = &at91_adc_configure_trigger,
.try_reenable = &at91_adc_reenable_trigger,
};
@ -584,7 +583,6 @@ static int at91_adc_write_raw(struct iio_dev *indio_dev,
static const struct iio_info at91_adc_info = {
.read_raw = &at91_adc_read_raw,
.write_raw = &at91_adc_write_raw,
.driver_module = THIS_MODULE,
};
static void at91_adc_hw_init(struct at91_adc_state *st)

2
drivers/iio/adc/at91_adc.c
View File

@ -594,7 +594,6 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
}
static const struct iio_trigger_ops at91_adc_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = &at91_adc_configure_trigger,
};
@ -976,7 +975,6 @@ static int at91_adc_probe_pdata(struct at91_adc_state *st,
}
static const struct iio_info at91_adc_info = {
.driver_module = THIS_MODULE,
.read_raw = &at91_adc_read_raw,
};

2
drivers/iio/adc/axp20x_adc.c
View File

@ -464,12 +464,10 @@ static int axp20x_write_raw(struct iio_dev *indio_dev,
static const struct iio_info axp20x_adc_iio_info = {
.read_raw = axp20x_read_raw,
.write_raw = axp20x_write_raw,
.driver_module = THIS_MODULE,
};
static const struct iio_info axp22x_adc_iio_info = {
.read_raw = axp22x_read_raw,
.driver_module = THIS_MODULE,
};
static int axp20x_adc_rate(int rate)

1
drivers/iio/adc/axp288_adc.c
View File

@ -183,7 +183,6 @@ static int axp288_adc_set_state(struct regmap *regmap)
static const struct iio_info axp288_adc_iio_info = {
.read_raw = &axp288_adc_read_raw,
.driver_module = THIS_MODULE,
};
static int axp288_adc_probe(struct platform_device *pdev)

1
drivers/iio/adc/bcm_iproc_adc.c
View File

@ -492,7 +492,6 @@ static int iproc_adc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info iproc_adc_iio_info = {
.read_raw = &iproc_adc_read_raw,
.driver_module = THIS_MODULE,
};
#define IPROC_ADC_CHANNEL(_index, _id) { \

1
drivers/iio/adc/berlin2-adc.c
View File

@ -277,7 +277,6 @@ static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
}
static const struct iio_info berlin2_adc_info = {
.driver_module = THIS_MODULE,
.read_raw = berlin2_adc_read_raw,
};

1
drivers/iio/adc/cc10001_adc.c
View File

@ -262,7 +262,6 @@ static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
}
static const struct iio_info cc10001_adc_info = {
.driver_module = THIS_MODULE,
.read_raw = &cc10001_adc_read_raw,
.update_scan_mode = &cc10001_update_scan_mode,
};

1
drivers/iio/adc/cpcap-adc.c
View File

@ -932,7 +932,6 @@ err_unlock:
static const struct iio_info cpcap_adc_info = {
.read_raw = &cpcap_adc_read,
.driver_module = THIS_MODULE,
};
/*

1
drivers/iio/adc/da9150-gpadc.c
View File

@ -249,7 +249,6 @@ static int da9150_gpadc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info da9150_gpadc_info = {
.read_raw = &da9150_gpadc_read_raw,
.driver_module = THIS_MODULE,
};
#define DA9150_GPADC_CHANNEL(_id, _hw_id, _type, chan_info, \

6
drivers/iio/adc/dln2-adc.c
View File

@ -479,7 +479,6 @@ static const struct iio_info dln2_adc_info = {
.read_raw = dln2_adc_read_raw,
.write_raw = dln2_adc_write_raw,
.update_scan_mode = dln2_update_scan_mode,
.driver_module = THIS_MODULE,
};
static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
@ -604,10 +603,6 @@ static void dln2_adc_event(struct platform_device *pdev, u16 echo,
iio_trigger_poll(dln2->trig);
}
static const struct iio_trigger_ops dln2_adc_trigger_ops = {
.owner = THIS_MODULE,
};
static int dln2_adc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@ -665,7 +660,6 @@ static int dln2_adc_probe(struct platform_device *pdev)
dev_err(dev, "failed to allocate trigger\n");
return -ENOMEM;
}
dln2->trig->ops = &dln2_adc_trigger_ops;
iio_trigger_set_drvdata(dln2->trig, dln2);
devm_iio_trigger_register(dev, dln2->trig);
iio_trigger_set_immutable(indio_dev, dln2->trig);

1
drivers/iio/adc/envelope-detector.c
View File

@ -322,7 +322,6 @@ static const struct iio_chan_spec envelope_detector_iio_channel = {
static const struct iio_info envelope_detector_info = {
.read_raw = &envelope_detector_read_raw,
.driver_module = THIS_MODULE,
};
static int envelope_detector_probe(struct platform_device *pdev)

1
drivers/iio/adc/ep93xx_adc.c
View File

@ -150,7 +150,6 @@ static int ep93xx_read_raw(struct iio_dev *iiodev,
}
static const struct iio_info ep93xx_adc_info = {
.driver_module = THIS_MODULE,
.read_raw = ep93xx_read_raw,
};

1
drivers/iio/adc/exynos_adc.c
View File

@ -657,7 +657,6 @@ static int exynos_adc_reg_access(struct iio_dev *indio_dev,
static const struct iio_info exynos_adc_iio_info = {
.read_raw = &exynos_read_raw,
.debugfs_reg_access = &exynos_adc_reg_access,
.driver_module = THIS_MODULE,
};
#define ADC_CHANNEL(_index, _id) { \

1
drivers/iio/adc/hi8435.c
View File

@ -408,7 +408,6 @@ static const struct iio_chan_spec hi8435_channels[] = {
};
static const struct iio_info hi8435_info = {
.driver_module = THIS_MODULE,
.read_raw = hi8435_read_raw,
.read_event_config = hi8435_read_event_config,
.write_event_config = hi8435_write_event_config,

1
drivers/iio/adc/hx711.c
View File

@ -374,7 +374,6 @@ static const struct attribute_group hx711_attribute_group = {
};
static const struct iio_info hx711_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = hx711_read_raw,
.write_raw = hx711_write_raw,
.write_raw_get_fmt = hx711_write_raw_get_fmt,

1
drivers/iio/adc/imx7d_adc.c
View File

@ -412,7 +412,6 @@ static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
}
static const struct iio_info imx7d_adc_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = &imx7d_adc_read_raw,
.debugfs_reg_access = &imx7d_adc_reg_access,
};

20
drivers/iio/adc/ina2xx-adc.c
View File

@ -123,7 +123,7 @@ struct ina2xx_chip_info {
struct task_struct *task;
const struct ina2xx_config *config;
struct mutex state_lock;
unsigned int shunt_resistor;
unsigned int shunt_resistor_uohm;
int avg;
int int_time_vbus; /* Bus voltage integration time uS */
int int_time_vshunt; /* Shunt voltage integration time uS */
@ -436,7 +436,7 @@ static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
/*
* Set current LSB to 1mA, shunt is in uOhms
* (equation 13 in datasheet). We hardcode a Current_LSB
* of 1.0 x10-6. The only remaining parameter is RShunt.
* of 1.0 x10-3. The only remaining parameter is RShunt.
* There is no need to expose the CALIBRATION register
* to the user for now. But we need to reset this register
* if the user updates RShunt after driver init, e.g upon
@ -445,7 +445,7 @@ static ssize_t ina2xx_allow_async_readout_store(struct device *dev,
static int ina2xx_set_calibration(struct ina2xx_chip_info *chip)
{
u16 regval = DIV_ROUND_CLOSEST(chip->config->calibration_factor,
chip->shunt_resistor);
chip->shunt_resistor_uohm);
return regmap_write(chip->regmap, INA2XX_CALIBRATION, regval);
}
@ -455,7 +455,7 @@ static int set_shunt_resistor(struct ina2xx_chip_info *chip, unsigned int val)
if (val <= 0 || val > chip->config->calibration_factor)
return -EINVAL;
chip->shunt_resistor = val;
chip->shunt_resistor_uohm = val;
return 0;
}
@ -465,8 +465,9 @@ static ssize_t ina2xx_shunt_resistor_show(struct device *dev,
char *buf)
{
struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
int vals[2] = { chip->shunt_resistor_uohm, 1000000 };
return sprintf(buf, "%d\n", chip->shunt_resistor);
return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals);
}
static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
@ -474,14 +475,13 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev,
const char *buf, size_t len)
{
struct ina2xx_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
unsigned long val;
int ret;
int val, val_fract, ret;
ret = kstrtoul((const char *) buf, 10, &val);
ret = iio_str_to_fixpoint(buf, 100000, &val, &val_fract);
if (ret)
return ret;
ret = set_shunt_resistor(chip, val);
ret = set_shunt_resistor(chip, val * 1000000 + val_fract);
if (ret)
return ret;
@ -778,7 +778,6 @@ static const struct attribute_group ina226_attribute_group = {
};
static const struct iio_info ina219_info = {
.driver_module = THIS_MODULE,
.attrs = &ina219_attribute_group,
.read_raw = ina2xx_read_raw,
.write_raw = ina2xx_write_raw,
@ -786,7 +785,6 @@ static const struct iio_info ina219_info = {
};
static const struct iio_info ina226_info = {
.driver_module = THIS_MODULE,
.attrs = &ina226_attribute_group,
.read_raw = ina2xx_read_raw,
.write_raw = ina2xx_write_raw,

1
drivers/iio/adc/lp8788_adc.c
View File

@ -125,7 +125,6 @@ static int lp8788_adc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info lp8788_adc_info = {
.read_raw = &lp8788_adc_read_raw,
.driver_module = THIS_MODULE,
};
#define LP8788_CHAN(_id, _type) { \

1
drivers/iio/adc/lpc18xx_adc.c
View File

@ -116,7 +116,6 @@ static int lpc18xx_adc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info lpc18xx_adc_info = {
.read_raw = lpc18xx_adc_read_raw,
.driver_module = THIS_MODULE,
};
static int lpc18xx_adc_probe(struct platform_device *pdev)

1
drivers/iio/adc/lpc32xx_adc.c
View File

@ -104,7 +104,6 @@ static int lpc32xx_read_raw(struct iio_dev *indio_dev,
static const struct iio_info lpc32xx_adc_iio_info = {
.read_raw = &lpc32xx_read_raw,
.driver_module = THIS_MODULE,
};
#define LPC32XX_ADC_CHANNEL(_index) { \

1
drivers/iio/adc/ltc2471.c
View File

@ -98,7 +98,6 @@ static const struct iio_chan_spec ltc2473_channel[] = {
static const struct iio_info ltc2471_info = {
.read_raw = ltc2471_read_raw,
.driver_module = THIS_MODULE,
};
static int ltc2471_i2c_probe(struct i2c_client *client,

1
drivers/iio/adc/ltc2485.c
View File

@ -90,7 +90,6 @@ static const struct iio_chan_spec ltc2485_channel[] = {
static const struct iio_info ltc2485_info = {
.read_raw = ltc2485_read_raw,
.driver_module = THIS_MODULE,
};
static int ltc2485_probe(struct i2c_client *client,

1
drivers/iio/adc/ltc2497.c
View File

@ -186,7 +186,6 @@ static const struct iio_chan_spec ltc2497_channel[] = {
static const struct iio_info ltc2497_info = {
.read_raw = ltc2497_read_raw,
.driver_module = THIS_MODULE,
};
static int ltc2497_probe(struct i2c_client *client,

2
drivers/iio/adc/max1027.c
View File

@ -381,13 +381,11 @@ static irqreturn_t max1027_trigger_handler(int irq, void *private)
}
static const struct iio_trigger_ops max1027_trigger_ops = {
.owner = THIS_MODULE,
.validate_device = &iio_trigger_validate_own_device,
.set_trigger_state = &max1027_set_trigger_state,
};
static const struct iio_info max1027_info = {
.driver_module = THIS_MODULE,
.read_raw = &max1027_read_raw,
.validate_trigger = &max1027_validate_trigger,
.debugfs_reg_access = &max1027_debugfs_reg_access,

1
drivers/iio/adc/max11100.c
View File

@ -100,7 +100,6 @@ static int max11100_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info max11100_info = {
.driver_module = THIS_MODULE,
.read_raw = max11100_read_raw,
};

1
drivers/iio/adc/max1118.c
View File

@ -155,7 +155,6 @@ static int max1118_read_raw(struct iio_dev *indio_dev,
static const struct iio_info max1118_info = {
.read_raw = max1118_read_raw,
.driver_module = THIS_MODULE,
};
static irqreturn_t max1118_trigger_handler(int irq, void *p)

2
drivers/iio/adc/max1363.c
View File

@ -1029,7 +1029,6 @@ static int max1363_update_scan_mode(struct iio_dev *indio_dev,
static const struct iio_info max1238_info = {
.read_raw = &max1363_read_raw,
.driver_module = THIS_MODULE,
.update_scan_mode = &max1363_update_scan_mode,
};
@ -1040,7 +1039,6 @@ static const struct iio_info max1363_info = {
.write_event_config = &max1363_write_event_config,
.read_raw = &max1363_read_raw,
.update_scan_mode = &max1363_update_scan_mode,
.driver_module = THIS_MODULE,
.event_attrs = &max1363_event_attribute_group,
};

2
drivers/iio/adc/max9611.c
View File

@ -460,7 +460,6 @@ static const struct attribute_group max9611_attribute_group = {
};
static const struct iio_info indio_info = {
.driver_module = THIS_MODULE,
.read_raw = max9611_read_raw,
.attrs = &max9611_attribute_group,
};
@ -573,7 +572,6 @@ static int max9611_probe(struct i2c_client *client,
static struct i2c_driver max9611_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = max9611_of_table,
},
.probe = max9611_probe,

237
drivers/iio/adc/mcp320x.c
View File

@ -19,6 +19,11 @@
* ------------
* 13 bit converter
* MCP3301
* ------------
* 22 bit converter
* MCP3550
* MCP3551
* MCP3553
*
* Datasheet can be found here:
* http://ww1.microchip.com/downloads/en/DeviceDoc/21293C.pdf mcp3001
@ -28,6 +33,7 @@
* http://ww1.microchip.com/downloads/en/DeviceDoc/21034D.pdf mcp3202
* http://ww1.microchip.com/downloads/en/DeviceDoc/21298c.pdf mcp3204/08
* http://ww1.microchip.com/downloads/en/DeviceDoc/21700E.pdf mcp3301
* http://ww1.microchip.com/downloads/en/DeviceDoc/21950D.pdf mcp3550/1/3
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -51,25 +57,45 @@ enum {
mcp3204,
mcp3208,
mcp3301,
mcp3550_50,
mcp3550_60,
mcp3551,
mcp3553,
};
struct mcp320x_chip_info {
const struct iio_chan_spec *channels;
unsigned int num_channels;
unsigned int resolution;
unsigned int conv_time; /* usec */
};
/**
* struct mcp320x - Microchip SPI ADC instance
* @spi: SPI slave (parent of the IIO device)
* @msg: SPI message to select a channel and receive a value from the ADC
* @transfer: SPI transfers used by @msg
* @start_conv_msg: SPI message to start a conversion by briefly asserting CS
* @start_conv_transfer: SPI transfer used by @start_conv_msg
* @reg: regulator generating Vref
* @lock: protects read sequences
* @chip_info: ADC properties
* @tx_buf: buffer for @transfer[0] (not used on single-channel converters)
* @rx_buf: buffer for @transfer[1]
*/
struct mcp320x {
struct spi_device *spi;
struct spi_message msg;
struct spi_transfer transfer[2];
struct spi_message start_conv_msg;
struct spi_transfer start_conv_transfer;
struct regulator *reg;
struct mutex lock;
const struct mcp320x_chip_info *chip_info;
u8 tx_buf ____cacheline_aligned;
u8 rx_buf[2];
u8 rx_buf[4];
};
static int mcp320x_channel_to_tx_data(int device_index,
@ -78,10 +104,6 @@ static int mcp320x_channel_to_tx_data(int device_index,
int start_bit = 1;
switch (device_index) {
case mcp3001:
case mcp3201:
case mcp3301:
return 0;
case mcp3002:
case mcp3202:
return ((start_bit << 4) | (!differential << 3) |
@ -102,21 +124,24 @@ static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
{
int ret;
adc->rx_buf[0] = 0;
adc->rx_buf[1] = 0;
adc->tx_buf = mcp320x_channel_to_tx_data(device_index,
channel, differential);
if (adc->chip_info->conv_time) {
ret = spi_sync(adc->spi, &adc->start_conv_msg);
if (ret < 0)
return ret;
if (device_index != mcp3001 && device_index != mcp3201 && device_index != mcp3301) {
ret = spi_sync(adc->spi, &adc->msg);
if (ret < 0)
return ret;
} else {
ret = spi_read(adc->spi, &adc->rx_buf, sizeof(adc->rx_buf));
if (ret < 0)
return ret;
usleep_range(adc->chip_info->conv_time,
adc->chip_info->conv_time + 100);
}
memset(&adc->rx_buf, 0, sizeof(adc->rx_buf));
if (adc->chip_info->num_channels > 1)
adc->tx_buf = mcp320x_channel_to_tx_data(device_index, channel,
differential);
ret = spi_sync(adc->spi, &adc->msg);
if (ret < 0)
return ret;
switch (device_index) {
case mcp3001:
*val = (adc->rx_buf[0] << 5 | adc->rx_buf[1] >> 3);
@ -138,6 +163,31 @@ static int mcp320x_adc_conversion(struct mcp320x *adc, u8 channel,
*val = sign_extend32((adc->rx_buf[0] & 0x1f) << 8
| adc->rx_buf[1], 12);
return 0;
case mcp3550_50:
case mcp3550_60:
case mcp3551:
case mcp3553: {
u32 raw = be32_to_cpup((u32 *)adc->rx_buf);
if (!(adc->spi->mode & SPI_CPOL))
raw <<= 1; /* strip Data Ready bit in SPI mode 0,0 */
/*
* If the input is within -vref and vref, bit 21 is the sign.
* Up to 12% overrange or underrange are allowed, in which case
* bit 23 is the sign and bit 0 to 21 is the value.
*/
raw >>= 8;
if (raw & BIT(22) && raw & BIT(23))
return -EIO; /* cannot have overrange AND underrange */
else if (raw & BIT(22))
raw &= ~BIT(22); /* overrange */
else if (raw & BIT(23) || raw & BIT(21))
raw |= GENMASK(31, 22); /* underrange or negative */
*val = (s32)raw;
return 0;
}
default:
return -EINVAL;
}
@ -248,7 +298,6 @@ static const struct iio_chan_spec mcp3208_channels[] = {
static const struct iio_info mcp320x_info = {
.read_raw = mcp320x_read_raw,
.driver_module = THIS_MODULE,
};
static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
@ -297,6 +346,31 @@ static const struct mcp320x_chip_info mcp320x_chip_infos[] = {
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 13
},
[mcp3550_50] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
/* 2% max deviation + 144 clock periods to exit shutdown */
.conv_time = 80000 * 1.02 + 144000 / 102.4,
},
[mcp3550_60] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 66670 * 1.02 + 144000 / 122.88,
},
[mcp3551] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 73100 * 1.02 + 144000 / 112.64,
},
[mcp3553] = {
.channels = mcp3201_channels,
.num_channels = ARRAY_SIZE(mcp3201_channels),
.resolution = 21,
.conv_time = 16670 * 1.02 + 144000 / 122.88,
},
};
static int mcp320x_probe(struct spi_device *spi)
@ -304,7 +378,7 @@ static int mcp320x_probe(struct spi_device *spi)
struct iio_dev *indio_dev;
struct mcp320x *adc;
const struct mcp320x_chip_info *chip_info;
int ret;
int ret, device_index;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
if (!indio_dev)
@ -320,7 +394,8 @@ static int mcp320x_probe(struct spi_device *spi)
indio_dev->info = &mcp320x_info;
spi_set_drvdata(spi, indio_dev);
chip_info = &mcp320x_chip_infos[spi_get_device_id(spi)->driver_data];
device_index = spi_get_device_id(spi)->driver_data;
chip_info = &mcp320x_chip_infos[device_index];
indio_dev->channels = chip_info->channels;
indio_dev->num_channels = chip_info->num_channels;
@ -329,10 +404,41 @@ static int mcp320x_probe(struct spi_device *spi)
adc->transfer[0].tx_buf = &adc->tx_buf;
adc->transfer[0].len = sizeof(adc->tx_buf);
adc->transfer[1].rx_buf = adc->rx_buf;
adc->transfer[1].len = sizeof(adc->rx_buf);
adc->transfer[1].len = DIV_ROUND_UP(chip_info->resolution, 8);
spi_message_init_with_transfers(&adc->msg, adc->transfer,
ARRAY_SIZE(adc->transfer));
if (chip_info->num_channels == 1)
/* single-channel converters are rx only (no MOSI pin) */
spi_message_init_with_transfers(&adc->msg,
&adc->transfer[1], 1);
else
spi_message_init_with_transfers(&adc->msg, adc->transfer,
ARRAY_SIZE(adc->transfer));
switch (device_index) {
case mcp3550_50:
case mcp3550_60:
case mcp3551:
case mcp3553:
/* rx len increases from 24 to 25 bit in SPI mode 0,0 */
if (!(spi->mode & SPI_CPOL))
adc->transfer[1].len++;
/* conversions are started by asserting CS pin for 8 usec */
adc->start_conv_transfer.delay_usecs = 8;
spi_message_init_with_transfers(&adc->start_conv_msg,
&adc->start_conv_transfer, 1);
/*
* If CS was previously kept low (continuous conversion mode)
* and then changed to high, the chip is in shutdown.
* Sometimes it fails to wake from shutdown and clocks out
* only 0xffffff. The magic sequence of performing two
* conversions without delay between them resets the chip
* and ensures all subsequent conversions succeed.
*/
mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
mcp320x_adc_conversion(adc, 0, 1, device_index, &ret);
}
adc->reg = devm_regulator_get(&spi->dev, "vref");
if (IS_ERR(adc->reg))
@ -370,62 +476,29 @@ static int mcp320x_remove(struct spi_device *spi)
#if defined(CONFIG_OF)
static const struct of_device_id mcp320x_dt_ids[] = {
/* NOTE: The use of compatibles with no vendor prefix is deprecated. */
{
.compatible = "mcp3001",
.data = &mcp320x_chip_infos[mcp3001],
}, {
.compatible = "mcp3002",
.data = &mcp320x_chip_infos[mcp3002],
}, {
.compatible = "mcp3004",
.data = &mcp320x_chip_infos[mcp3004],
}, {
.compatible = "mcp3008",
.data = &mcp320x_chip_infos[mcp3008],
}, {
.compatible = "mcp3201",
.data = &mcp320x_chip_infos[mcp3201],
}, {
.compatible = "mcp3202",
.data = &mcp320x_chip_infos[mcp3202],
}, {
.compatible = "mcp3204",
.data = &mcp320x_chip_infos[mcp3204],
}, {
.compatible = "mcp3208",
.data = &mcp320x_chip_infos[mcp3208],
}, {
.compatible = "mcp3301",
.data = &mcp320x_chip_infos[mcp3301],
}, {
.compatible = "microchip,mcp3001",
.data = &mcp320x_chip_infos[mcp3001],
}, {
.compatible = "microchip,mcp3002",
.data = &mcp320x_chip_infos[mcp3002],
}, {
.compatible = "microchip,mcp3004",
.data = &mcp320x_chip_infos[mcp3004],
}, {
.compatible = "microchip,mcp3008",
.data = &mcp320x_chip_infos[mcp3008],
}, {
.compatible = "microchip,mcp3201",
.data = &mcp320x_chip_infos[mcp3201],
}, {
.compatible = "microchip,mcp3202",
.data = &mcp320x_chip_infos[mcp3202],
}, {
.compatible = "microchip,mcp3204",
.data = &mcp320x_chip_infos[mcp3204],
}, {
.compatible = "microchip,mcp3208",
.data = &mcp320x_chip_infos[mcp3208],
}, {
.compatible = "microchip,mcp3301",
.data = &mcp320x_chip_infos[mcp3301],
}, {
}
{ .compatible = "mcp3001" },
{ .compatible = "mcp3002" },
{ .compatible = "mcp3004" },
{ .compatible = "mcp3008" },
{ .compatible = "mcp3201" },
{ .compatible = "mcp3202" },
{ .compatible = "mcp3204" },
{ .compatible = "mcp3208" },
{ .compatible = "mcp3301" },
{ .compatible = "microchip,mcp3001" },
{ .compatible = "microchip,mcp3002" },
{ .compatible = "microchip,mcp3004" },
{ .compatible = "microchip,mcp3008" },
{ .compatible = "microchip,mcp3201" },
{ .compatible = "microchip,mcp3202" },
{ .compatible = "microchip,mcp3204" },
{ .compatible = "microchip,mcp3208" },
{ .compatible = "microchip,mcp3301" },
{ .compatible = "microchip,mcp3550-50" },
{ .compatible = "microchip,mcp3550-60" },
{ .compatible = "microchip,mcp3551" },
{ .compatible = "microchip,mcp3553" },
{ }
};
MODULE_DEVICE_TABLE(of, mcp320x_dt_ids);
#endif
@ -440,6 +513,10 @@ static const struct spi_device_id mcp320x_id[] = {
{ "mcp3204", mcp3204 },
{ "mcp3208", mcp3208 },
{ "mcp3301", mcp3301 },
{ "mcp3550-50", mcp3550_50 },
{ "mcp3550-60", mcp3550_60 },
{ "mcp3551", mcp3551 },
{ "mcp3553", mcp3553 },
{ }
};
MODULE_DEVICE_TABLE(spi, mcp320x_id);
@ -456,5 +533,5 @@ static struct spi_driver mcp320x_driver = {
module_spi_driver(mcp320x_driver);
MODULE_AUTHOR("Oskar Andero <oskar.andero@gmail.com>");
MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08");
MODULE_DESCRIPTION("Microchip Technology MCP3x01/02/04/08 and MCP3550/1/3");
MODULE_LICENSE("GPL v2");

1
drivers/iio/adc/mcp3422.c
View File

@ -327,7 +327,6 @@ static const struct iio_info mcp3422_info = {
.write_raw = mcp3422_write_raw,
.write_raw_get_fmt = mcp3422_write_raw_get_fmt,
.attrs = &mcp3422_attribute_group,
.driver_module = THIS_MODULE,
};
static int mcp3422_probe(struct i2c_client *client,

1
drivers/iio/adc/men_z188_adc.c
View File

@ -80,7 +80,6 @@ static int z188_iio_read_raw(struct iio_dev *iio_dev,
static const struct iio_info z188_adc_info = {
.read_raw = &z188_iio_read_raw,
.driver_module = THIS_MODULE,
};
static void men_z188_config_channels(void __iomem *addr)

1
drivers/iio/adc/meson_saradc.c
View File

@ -840,7 +840,6 @@ out:
static const struct iio_info meson_sar_adc_iio_info = {
.read_raw = meson_sar_adc_iio_info_read_raw,
.driver_module = THIS_MODULE,
};
static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {

2
drivers/iio/adc/mt6577_auxadc.c
View File

@ -180,7 +180,6 @@ static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev,
}
static const struct iio_info mt6577_auxadc_info = {
.driver_module = THIS_MODULE,
.read_raw = &mt6577_auxadc_read_raw,
};
@ -306,6 +305,7 @@ static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
static const struct of_device_id mt6577_auxadc_of_match[] = {
{ .compatible = "mediatek,mt2701-auxadc", },
{ .compatible = "mediatek,mt2712-auxadc", },
{ .compatible = "mediatek,mt7622-auxadc", },
{ .compatible = "mediatek,mt8173-auxadc", },
{ }

2
drivers/iio/adc/mxs-lradc-adc.c
View File

@ -382,7 +382,6 @@ static const struct attribute_group mxs_lradc_adc_attribute_group = {
};
static const struct iio_info mxs_lradc_adc_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = mxs_lradc_adc_read_raw,
.write_raw = mxs_lradc_adc_write_raw,
.write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
@ -455,7 +454,6 @@ static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
}
static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
.owner = THIS_MODULE,
.set_trigger_state = &mxs_lradc_adc_configure_trigger,
};

1
drivers/iio/adc/nau7802.c
View File

@ -402,7 +402,6 @@ static int nau7802_write_raw_get_fmt(struct iio_dev *indio_dev,
}
static const struct iio_info nau7802_info = {
.driver_module = THIS_MODULE,
.read_raw = &nau7802_read_raw,
.write_raw = &nau7802_write_raw,
.write_raw_get_fmt = nau7802_write_raw_get_fmt,

1
drivers/iio/adc/palmas_gpadc.c
View File

@ -430,7 +430,6 @@ out:
static const struct iio_info palmas_gpadc_iio_info = {
.read_raw = palmas_gpadc_read_raw,
.driver_module = THIS_MODULE,
};
#define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \

1
drivers/iio/adc/qcom-pm8xxx-xoadc.c
View File

@ -728,7 +728,6 @@ static int pm8xxx_of_xlate(struct iio_dev *indio_dev,
}
static const struct iio_info pm8xxx_xoadc_info = {
.driver_module = THIS_MODULE,
.of_xlate = pm8xxx_of_xlate,
.read_raw = pm8xxx_read_raw,
};

1
drivers/iio/adc/qcom-spmi-iadc.c
View File

@ -356,7 +356,6 @@ static int iadc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info iadc_info = {
.read_raw = iadc_read_raw,
.driver_module = THIS_MODULE,
};
static irqreturn_t iadc_isr(int irq, void *dev_id)

1
drivers/iio/adc/qcom-spmi-vadc.c
View File

@ -506,7 +506,6 @@ static int vadc_of_xlate(struct iio_dev *indio_dev,
static const struct iio_info vadc_info = {
.read_raw = vadc_read_raw,
.of_xlate = vadc_of_xlate,
.driver_module = THIS_MODULE,
};
struct vadc_channels {

8
drivers/iio/adc/rcar-gyroadc.c
View File

@ -277,7 +277,6 @@ static int rcar_gyroadc_reg_access(struct iio_dev *indio_dev,
}
static const struct iio_info rcar_gyroadc_iio_info = {
.driver_module = THIS_MODULE,
.read_raw = rcar_gyroadc_read_raw,
.debugfs_reg_access = rcar_gyroadc_reg_access,
};
@ -349,7 +348,7 @@ static int rcar_gyroadc_parse_subdevs(struct iio_dev *indio_dev)
continue;
}
childmode = (unsigned int)of_id->data;
childmode = (uintptr_t)of_id->data;
switch (childmode) {
case RCAR_GYROADC_MODE_SELECT_1_MB88101A:
sample_width = 12;
@ -488,8 +487,6 @@ err:
static int rcar_gyroadc_probe(struct platform_device *pdev)
{
const struct of_device_id *of_id =
of_match_device(rcar_gyroadc_match, &pdev->dev);
struct device *dev = &pdev->dev;
struct rcar_gyroadc *priv;
struct iio_dev *indio_dev;
@ -526,7 +523,8 @@ static int rcar_gyroadc_probe(struct platform_device *pdev)
if (ret)
return ret;
priv->model = (enum rcar_gyroadc_model)of_id->data;
priv->model = (enum rcar_gyroadc_model)
of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, indio_dev);

1
drivers/iio/adc/rockchip_saradc.c
View File

@ -125,7 +125,6 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
static const struct iio_info rockchip_saradc_iio_info = {
.read_raw = rockchip_saradc_read_raw,
.driver_module = THIS_MODULE,
};
#define ADC_CHANNEL(_index, _id) { \

1
drivers/iio/adc/spear_adc.c
View File

@ -254,7 +254,6 @@ static int spear_adc_configure(struct spear_adc_state *st)
static const struct iio_info spear_adc_info = {
.read_raw = &spear_adc_read_raw,
.write_raw = &spear_adc_write_raw,
.driver_module = THIS_MODULE,
};
static int spear_adc_probe(struct platform_device *pdev)

13
drivers/iio/adc/stm32-adc-core.c
View File

@ -139,6 +139,11 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
}
rate = clk_get_rate(priv->aclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid clock rate: 0\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
break;
@ -216,6 +221,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
* From spec: PLL output musn't exceed max rate
*/
rate = clk_get_rate(priv->aclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
@ -232,6 +241,10 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
/* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
rate = clk_get_rate(priv->bclk);
if (!rate) {
dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
return -EINVAL;
}
for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;

2
drivers/iio/adc/stm32-adc.c
View File

@ -531,6 +531,7 @@ static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
{ TIM2_TRGO, STM32_EXT11 },
{ TIM4_TRGO, STM32_EXT12 },
{ TIM6_TRGO, STM32_EXT13 },
{ TIM15_TRGO, STM32_EXT14 },
{ TIM3_CH4, STM32_EXT15 },
{ LPTIM1_OUT, STM32_EXT18 },
{ LPTIM2_OUT, STM32_EXT19 },
@ -1385,7 +1386,6 @@ static const struct iio_info stm32_adc_iio_info = {
.update_scan_mode = stm32_adc_update_scan_mode,
.debugfs_reg_access = stm32_adc_debugfs_reg_access,
.of_xlate = stm32_adc_of_xlate,
.driver_module = THIS_MODULE,
};
static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)

1
drivers/iio/adc/stx104.c
View File

@ -172,7 +172,6 @@ static int stx104_write_raw(struct iio_dev *indio_dev,
}
static const struct iio_info stx104_info = {
.driver_module = THIS_MODULE,
.read_raw = stx104_read_raw,
.write_raw = stx104_write_raw
};

45
drivers/iio/adc/sun4i-gpadc-iio.c
View File

@ -352,7 +352,6 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
static const struct iio_info sun4i_gpadc_iio_info = {
.read_raw = sun4i_gpadc_read_raw,
.driver_module = THIS_MODULE,
};
static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id)
@ -502,17 +501,15 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
struct iio_dev *indio_dev)
{
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
const struct of_device_id *of_dev;
struct resource *mem;
void __iomem *base;
int ret;
of_dev = of_match_device(sun4i_gpadc_of_id, &pdev->dev);
if (!of_dev)
info->data = of_device_get_match_data(&pdev->dev);
if (!info->data)
return -ENODEV;
info->no_irq = true;
info->data = (struct gpadc_data *)of_dev->data;
indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
indio_dev->channels = sun8i_a33_gpadc_channels;
@ -529,17 +526,10 @@ static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
return ret;
}
if (!IS_ENABLED(CONFIG_THERMAL_OF))
return 0;
if (IS_ENABLED(CONFIG_THERMAL_OF))
info->sensor_device = &pdev->dev;
info->sensor_device = &pdev->dev;
info->tzd = thermal_zone_of_sensor_register(info->sensor_device, 0,
info, &sun4i_ts_tz_ops);
if (IS_ERR(info->tzd))
dev_err(&pdev->dev, "could not register thermal sensor: %ld\n",
PTR_ERR(info->tzd));
return PTR_ERR_OR_ZERO(info->tzd);
return 0;
}
static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
@ -586,15 +576,6 @@ static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
* return the temperature.
*/
info->sensor_device = pdev->dev.parent;
info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
0, info,
&sun4i_ts_tz_ops);
if (IS_ERR(info->tzd)) {
dev_err(&pdev->dev,
"could not register thermal sensor: %ld\n",
PTR_ERR(info->tzd));
return PTR_ERR(info->tzd);
}
} else {
indio_dev->num_channels =
ARRAY_SIZE(sun4i_gpadc_channels_no_temp);
@ -664,6 +645,22 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)
pm_runtime_set_suspended(&pdev->dev);
pm_runtime_enable(&pdev->dev);
if (IS_ENABLED(CONFIG_THERMAL_OF)) {
info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
0, info,
&sun4i_ts_tz_ops);
/*
* Do not fail driver probing when failing to register in
* thermal because no thermal DT node is found.
*/
if (IS_ERR(info->tzd) && PTR_ERR(info->tzd) != -ENODEV) {
dev_err(&pdev->dev,
"could not register thermal sensor: %ld\n",
PTR_ERR(info->tzd));
return PTR_ERR(info->tzd);
}
}
ret = devm_iio_device_register(&pdev->dev, indio_dev);
if (ret < 0) {
dev_err(&pdev->dev, "could not register the device\n");

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