x86: Add NumaChip support
Adds support for Numascale NumaChip large-SMP systems. It is needed to enable the booting of more than ~168 cores. v2: - [Steffen] enumerate only accessible northbridges - [Daniel] rediffed and validated against 3.1-rc10 v3: - [Daniel] use x86_init core numbering override - [Daniel] cleanups as per feedback v4: - [Daniel] use updated x86_cpuinit override v5: - drop disabling interrupts locally, as ISR write is atomic; drop delay - added read-mostly annotations where appropriate - require CONFIG_SMP, so drop conditional path Workload tested on 96 cores/16 sockets. Signed-off-by: Steffen Persvold <sp@numascale.com> Signed-off-by: Daniel J Blueman <daniel@numascale-asia.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Link: http://lkml.kernel.org/r/1323101246-2400-1-git-send-email-daniel@numascale-asia.com Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Steffen Persvold
Ingo Molnar
parent
64be4c1c24
commit
44b111b519
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@ -343,6 +343,7 @@ config X86_EXTENDED_PLATFORM
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If you enable this option then you'll be able to select support
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for the following (non-PC) 64 bit x86 platforms:
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Numascale NumaChip
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ScaleMP vSMP
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SGI Ultraviolet
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@ -351,6 +352,18 @@ config X86_EXTENDED_PLATFORM
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endif
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# This is an alphabetically sorted list of 64 bit extended platforms
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# Please maintain the alphabetic order if and when there are additions
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config X86_NUMACHIP
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bool "Numascale NumaChip"
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depends on X86_64
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depends on X86_EXTENDED_PLATFORM
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depends on NUMA
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depends on SMP
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depends on X86_X2APIC
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depends on !EDAC_AMD64
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---help---
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Adds support for Numascale NumaChip large-SMP systems. Needed to
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enable more than ~168 cores.
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If you don't have one of these, you should say N here.
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config X86_VSMP
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bool "ScaleMP vSMP"
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@ -0,0 +1,167 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-Specific Header file
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*
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* Copyright (C) 2011 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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*/
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#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
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#include <linux/numa.h>
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#include <linux/percpu.h>
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#include <linux/io.h>
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#include <linux/swab.h>
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#include <asm/types.h>
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#include <asm/processor.h>
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#define CSR_NODE_SHIFT 16
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#define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
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#define CSR_NODE_MASK 0x0fff /* 4K nodes */
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/* 32K CSR space, b15 indicates geo/non-geo */
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#define CSR_OFFSET_MASK 0x7fffUL
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/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
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#define NUMACHIP_GCSR_BASE 0x3fff00000000ULL
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#define NUMACHIP_GCSR_LIM 0x3fff0fffffffULL
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#define NUMACHIP_GCSR_SIZE (NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)
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/*
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* Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
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* when using the direct mapping on x86_64, both start and size needs to be
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* aligned with PMD_SIZE which is 2M
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*/
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#define NUMACHIP_LCSR_BASE 0x3ffffe000000ULL
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#define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
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#define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
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static inline void *gcsr_address(int node, unsigned long offset)
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{
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return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |
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CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));
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}
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static inline void *lcsr_address(unsigned long offset)
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{
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return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
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CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
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}
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static inline unsigned int read_gcsr(int node, unsigned long offset)
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{
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return swab32(readl(gcsr_address(node, offset)));
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}
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static inline void write_gcsr(int node, unsigned long offset, unsigned int val)
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{
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writel(swab32(val), gcsr_address(node, offset));
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}
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static inline unsigned int read_lcsr(unsigned long offset)
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{
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return swab32(readl(lcsr_address(offset)));
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}
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static inline void write_lcsr(unsigned long offset, unsigned int val)
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{
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writel(swab32(val), lcsr_address(offset));
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}
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/* ========================================================================= */
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/* CSR_G0_STATE_CLEAR */
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/* ========================================================================= */
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#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))
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union numachip_csr_g0_state_clear {
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unsigned int v;
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struct numachip_csr_g0_state_clear_s {
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unsigned int _state:2;
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unsigned int _rsvd_2_6:5;
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unsigned int _lost:1;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G0_NODE_IDS */
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/* ========================================================================= */
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#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
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union numachip_csr_g0_node_ids {
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unsigned int v;
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struct numachip_csr_g0_node_ids_s {
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unsigned int _initialid:16;
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unsigned int _nodeid:12;
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unsigned int _rsvd_28_31:4;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_GEN */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
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union numachip_csr_g3_ext_irq_gen {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_gen_s {
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unsigned int _vector:8;
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unsigned int _msgtype:3;
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unsigned int _index:5;
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unsigned int _destination_apic_id:16;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_STATUS */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))
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union numachip_csr_g3_ext_irq_status {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_status_s {
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unsigned int _result:32;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_EXT_IRQ_DEST */
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/* ========================================================================= */
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#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))
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union numachip_csr_g3_ext_irq_dest {
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unsigned int v;
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struct numachip_csr_g3_ext_irq_dest_s {
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unsigned int _irq:8;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_NC_ATT_MAP_SELECT */
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/* ========================================================================= */
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#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))
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union numachip_csr_g3_nc_att_map_select {
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unsigned int v;
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struct numachip_csr_g3_nc_att_map_select_s {
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unsigned int _upper_address_bits:4;
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unsigned int _select_ram:4;
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unsigned int _rsvd_8_31:24;
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} s;
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};
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/* ========================================================================= */
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/* CSR_G3_NC_ATT_MAP_SELECT_0-255 */
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/* ========================================================================= */
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#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))
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#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
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@ -10,6 +10,7 @@ obj-$(CONFIG_SMP) += ipi.o
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ifeq ($(CONFIG_X86_64),y)
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# APIC probe will depend on the listing order here
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obj-$(CONFIG_X86_NUMACHIP) += apic_numachip.o
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obj-$(CONFIG_X86_UV) += x2apic_uv_x.o
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obj-$(CONFIG_X86_X2APIC) += x2apic_phys.o
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obj-$(CONFIG_X86_X2APIC) += x2apic_cluster.o
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@ -0,0 +1,294 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-Specific APIC Code
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*
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* Copyright (C) 2011 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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*/
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#include <linux/errno.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/hardirq.h>
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#include <linux/delay.h>
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#include <asm/numachip/numachip_csr.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <asm/apic_flat_64.h>
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static int numachip_system __read_mostly;
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static struct apic apic_numachip __read_mostly;
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned long value;
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unsigned int id;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = ((id & 0xffU) << 24);
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return x;
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}
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static unsigned int read_xapic_id(void)
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{
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return get_apic_id(apic_read(APIC_ID));
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}
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static int numachip_apic_id_registered(void)
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{
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return physid_isset(read_xapic_id(), phys_cpu_present_map);
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}
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static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
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{
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return initial_apic_id >> index_msb;
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}
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static const struct cpumask *numachip_target_cpus(void)
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{
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return cpu_online_mask;
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}
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static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
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{
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union numachip_csr_g3_ext_irq_gen int_gen;
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int_gen.s._destination_apic_id = phys_apicid;
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int_gen.s._vector = 0;
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int_gen.s._msgtype = APIC_DM_INIT >> 8;
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int_gen.s._index = 0;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
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int_gen.s._vector = start_rip >> 12;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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atomic_set(&init_deasserted, 1);
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return 0;
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}
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static void numachip_send_IPI_one(int cpu, int vector)
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{
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union numachip_csr_g3_ext_irq_gen int_gen;
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int apicid = per_cpu(x86_cpu_to_apicid, cpu);
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int_gen.s._destination_apic_id = apicid;
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int_gen.s._vector = vector;
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int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
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int_gen.s._index = 0;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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}
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static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned int cpu;
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for_each_cpu(cpu, mask)
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numachip_send_IPI_one(cpu, vector);
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}
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static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
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int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_cpu(cpu, mask) {
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if (cpu != this_cpu)
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numachip_send_IPI_one(cpu, vector);
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}
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}
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static void numachip_send_IPI_allbutself(int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != this_cpu)
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numachip_send_IPI_one(cpu, vector);
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}
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}
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static void numachip_send_IPI_all(int vector)
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{
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numachip_send_IPI_mask(cpu_online_mask, vector);
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}
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static void numachip_send_IPI_self(int vector)
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{
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__default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
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}
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static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = cpumask_first(cpumask);
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if (likely((unsigned)cpu < nr_cpu_ids))
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return per_cpu(x86_cpu_to_apicid, cpu);
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return BAD_APICID;
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}
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static unsigned int
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numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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return per_cpu(x86_cpu_to_apicid, cpu);
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}
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static int __init numachip_probe(void)
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{
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return apic == &apic_numachip;
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}
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static void __init map_csrs(void)
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{
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printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
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NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
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init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
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printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
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NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
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init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
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}
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static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
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{
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c->phys_proc_id = node;
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per_cpu(cpu_llc_id, smp_processor_id()) = node;
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}
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static int __init numachip_system_init(void)
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{
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unsigned int val;
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if (!numachip_system)
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return 0;
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x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
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map_csrs();
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val = read_lcsr(CSR_G0_NODE_IDS);
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printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
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return 0;
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}
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early_initcall(numachip_system_init);
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static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (!strncmp(oem_id, "NUMASC", 6)) {
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numachip_system = 1;
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return 1;
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}
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return 0;
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}
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static struct apic apic_numachip __refconst = {
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.name = "NumaConnect system",
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.probe = numachip_probe,
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.acpi_madt_oem_check = numachip_acpi_madt_oem_check,
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.apic_id_registered = numachip_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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.irq_dest_mode = 0, /* physical */
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.target_cpus = numachip_target_cpus,
|
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.disable_esr = 0,
|
||||
.dest_logical = 0,
|
||||
.check_apicid_used = NULL,
|
||||
.check_apicid_present = NULL,
|
||||
|
||||
.vector_allocation_domain = numachip_vector_allocation_domain,
|
||||
.init_apic_ldr = flat_init_apic_ldr,
|
||||
|
||||
.ioapic_phys_id_map = NULL,
|
||||
.setup_apic_routing = NULL,
|
||||
.multi_timer_check = NULL,
|
||||
.cpu_present_to_apicid = default_cpu_present_to_apicid,
|
||||
.apicid_to_cpu_present = NULL,
|
||||
.setup_portio_remap = NULL,
|
||||
.check_phys_apicid_present = default_check_phys_apicid_present,
|
||||
.enable_apic_mode = NULL,
|
||||
.phys_pkg_id = numachip_phys_pkg_id,
|
||||
.mps_oem_check = NULL,
|
||||
|
||||
.get_apic_id = get_apic_id,
|
||||
.set_apic_id = set_apic_id,
|
||||
.apic_id_mask = 0xffU << 24,
|
||||
|
||||
.cpu_mask_to_apicid = numachip_cpu_mask_to_apicid,
|
||||
.cpu_mask_to_apicid_and = numachip_cpu_mask_to_apicid_and,
|
||||
|
||||
.send_IPI_mask = numachip_send_IPI_mask,
|
||||
.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
|
||||
.send_IPI_allbutself = numachip_send_IPI_allbutself,
|
||||
.send_IPI_all = numachip_send_IPI_all,
|
||||
.send_IPI_self = numachip_send_IPI_self,
|
||||
|
||||
.wakeup_secondary_cpu = numachip_wakeup_secondary,
|
||||
.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
|
||||
.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
|
||||
.wait_for_init_deassert = NULL,
|
||||
.smp_callin_clear_local_apic = NULL,
|
||||
.inquire_remote_apic = NULL, /* REMRD not supported */
|
||||
|
||||
.read = native_apic_mem_read,
|
||||
.write = native_apic_mem_write,
|
||||
.icr_read = native_apic_icr_read,
|
||||
.icr_write = native_apic_icr_write,
|
||||
.wait_icr_idle = native_apic_wait_icr_idle,
|
||||
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
|
||||
};
|
||||
apic_driver(apic_numachip);
|
||||
|
||||
Loading…
Reference in New Issue