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agp/intel: Reduce extraneous PCI posting reads during init 

Instead of doing a posting read after each GTT entry update, do a single one
at the end of the writes. This should reduce boot time a tiny amount by
avoiding a lot of extra uncached reads.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
hifive-unleashed-5.1
Keith Packard 2008-10-14 17:18:45 -07:00 committed by Dave Airlie
parent 82e14a6215
commit 44d4944172
1 changed files with 3 additions and 3 deletions
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6
drivers/char/agp/intel-agp.c
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@ -214,8 +214,8 @@ static int intel_i810_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = 0; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
}
readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
}
global_cache_flush();
return 0;
@ -775,8 +775,8 @@ static int intel_i830_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
}
readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
}
global_cache_flush();
@ -991,8 +991,8 @@ static int intel_i915_configure(void)
if (agp_bridge->driver->needs_scratch_page) {
for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
writel(agp_bridge->scratch_page, intel_private.gtt+i);
readl(intel_private.gtt+i); /* PCI Posting. */
}
readl(intel_private.gtt+i-1); /* PCI Posting. */
}
global_cache_flush();